公开(公告)号：WO2017156360A1

公开(公告)日：2017-09-14

申请号：PCT/US2017/021725

申请日：2017-03-10

Applicant: ANALOG DEVICES, INC.

Inventor： FOLEY, David P.

IPC: H03K5/135 ,  H03K5/133

Abstract: An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate a fine delayed rising edge signal from the coarse delayed rising edge signal and a fine delayed falling edge signal from the coarse delayed falling edge signal; an edge combiner configured to generate the timing signal based on the fine delayed rising edge signal and the fine delayed falling edge signal; and a masking circuit configured to generate a rising edge masking signal and a falling edge masking signal for controlling when the rising edges and the falling edges of the timing signal are generated.

Abstract translation: 示例性定时发生器包括：粗略延迟电路，其被配置为从参考定时信号生成粗略延迟上升沿信号和粗略延迟下降沿信号; 精细延迟电路，被配置为从所述粗略延迟上升沿信号和来自所述粗略延迟下降沿信号的精确延迟下降沿信号生成精细延迟上升沿信号; 边沿组合器，被配置为基于精延迟的上升沿信号和精延迟的下降沿信号来产生定时信号; 以及掩蔽电路，被配置为产生用于控制定时信号的上升沿和下降沿何时产生的上升沿掩蔽信号和下降沿掩蔽信号。

公开(公告)号：WO2023078674A1

公开(公告)日：2023-05-11

申请号：PCT/EP2022/078976

申请日：2022-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED

Inventor： BORKENHAGEN, John ,  KESSELRING, Grant ,  STROM, James ,  STEFFEN, Christopher

IPC: H03L7/085 ,  H03L7/089 ,  H03L7/093 ,  H03L7/14 ,  H03K5/133

Abstract: A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indicates that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer selection signal that selects one buffer of a plurality of buffers within the pulse limiter. The pulse limiter generates a second signal that indicates a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period that is associated with the pulse limiter buffer selection signal. The pulse limiter truncates the clock pulse to the truncated pulse width and sends the truncated clock pulse to the charge pump.

公开(公告)号：WO2018127721A1

公开(公告)日：2018-07-12

申请号：PCT/IB2017/000323

申请日：2017-03-16

Applicant: DISRUPTIVE TECHNOLOGIES RESEARCH AS ,  MOLDSVOR, Oystein

Inventor： HERNES, Bjørnar

IPC: H03K5/133 ,  H03K17/955 ,  G01D5/24 ,  G06F1/06 ,  H03K5/00

Abstract: A clock delay circuit is configured to generate a delayed clock signal based on an input clock signal, the delayed clock signal delayed by a delay time (T DEL ). The circuit includes a current mirror configured to generate starved currents based on the reference current, a plurality of inverters, and a Schmitt trigger configured to generate an output signal in response to the input clock signal, wherein the Schmitt trigger output signal increases from a low signal to a high signal over a period (T CHARGE ) correlated with T DEL . Some inverters and the Schmitt trigger are configured to be current starved when the input clock signal is high and are configured to be shorted to ground and the reference current when the input clock signal is low. T DEL is based on T CHARGE and T CHARGE is based on C, N TOP , V ST , High , and a supply voltage.

公开(公告)号：WO2017219039A1

公开(公告)日：2017-12-21

申请号：PCT/US2017/038183

申请日：2017-06-19

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： KAMATH, Anant, Shankar ,  J, Divyasree

IPC: H03K5/04 ,  H03K5/133

Abstract: In described examples of a communication system (10), the system (10) includes a data transmitter (12) configured to generate a digital communication signal and a data receiver (14) configured to receive the digital communication signal. The system (10) also includes a pulse-width distortion (PWD) correction circuit (20) arranged between the data transmitter (12) and the data receiver (14) and being configured to adjust at least one timing parameter associated with the communication signal.

Abstract translation: 在所描述的通信系统（10）的示例中，系统（10）包括被配置为生成数字通信信号的数据发射机（12）和被配置为接收数字通信信号的数据接收机（14） 通信信号。 系统（10）还包括布置在数据发送器（12）和数据接收器（14）之间的脉宽失真（PWD）校正电路（20），并且被配置为调整与通信信号相关联的至少一个定时参数

公开(公告)号：WO2016017872A1

公开(公告)日：2016-02-04

申请号：PCT/KR2014/012814

申请日：2014-12-24

Applicant: 중앙대학교 산학협력단

Inventor： 백광현 ,  이창우 ,  김주언 ,  윤선우

IPC: H03M1/38 ,  H03K5/133

CPC classification number: H03M1/38 ,  H03K5/134 ,  H03K2005/00195 ,  H03L7/00 ,  H03L7/0893 ,  H03L2207/06 ,  H03M1/125

Abstract: 비동기식 연속 근사 레지스터 아날로그 디지털 변환기 및 그에 포함되는 내부 클럭 발생기가 개시된다. 연속 근사 레지스터 아날로그 디지털 변환기에 포함되는 내부 클럭 발생기는, 최종 내부 클럭과 다음 외부 클럭의 발생 시점을 감지하여 업 펄스 또는 다운 펄스를 생성하는 검출부; 및 상기 업 펄스 또는 다운 펄스에 따라 바이어스 전압을 제어하여 지연 시간을 증가 또는 감소시키는 딜레이 블록을 포함한다.

Abstract translation: 公开了一种异步逐次逼近电阻模数转换器及其内部时钟发生器。 包括在逐次逼近电阻模数转换器中的内部时钟发生器包括：检测单元，用于通过感测产生最后内部时钟和后续外部时钟的时间点来产生上升脉冲或下降脉冲; 以及用于通过根据上升脉冲或下降脉冲控制偏置电压来增加或减少延迟时间的延迟模块。

公开(公告)号：WO2023048978A2

公开(公告)日：2023-03-30

申请号：PCT/US2022/043221

申请日：2022-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： BOWMAN, Keith Alan ,  YINGLING, Daniel ,  PAL, Dipti Ranjan

IPC: H03K5/156 ,  H03K5/05 ,  H03K5/00 ,  G06F1/10 ,  H03K5/131 ,  H03K5/133

Abstract: Aspects of the present disclosure relate to a duty-cycle adjuster (1220) including a first inverter (1235), a first multiplexer (1240), a high-phase extender (1250), a second inverter (1265), and a second multiplexer (1270). The first multiplexer (1240) has a first input (1242), a second input (1244), a select input (1246), and an output (1248). The first input (1242) of the first multiplexer (1240) is coupled to the signal input (1222) of the duty-cycle adjuster (1220), and the select input (1246) of the first multiplexer (1240) is coupled to the first control input (1226). The first inverter (1235) is coupled between the signal input (1222) of the duty-cycle adjuster (1220) and the second input (1244) of the first multiplexer (1240).

公开(公告)号：WO2023273748A1

公开(公告)日：2023-01-05

申请号：PCT/CN2022/095734

申请日：2022-05-27

Applicant: 澜起电子科技（昆山）有限公司

Inventor： 许文林 ,  江立新 ,  曲勃 ,  陈金福

IPC: H03K5/133

Abstract: 本发明提供一种延迟装置及延迟控制方法。延迟装置包括至少一个电流控制延迟组以及至少一个开关。所述至少一个电流控制延迟组耦接至传输线，每一电流控制延迟组包括至少一个电流控制延迟器，每一电流控制延迟器根据控制电压提供延迟。开关分别耦接在电流控制延迟组和传输导线之间，开关的每一个根据施加至其的使能信号的位被导通或断开。本发明可动态调整所产生的延迟，并且能够不受寄生电容的影响。

公开(公告)号：WO2022064893A1

公开(公告)日：2022-03-31

申请号：PCT/JP2021/029711

申请日：2021-08-12

Applicant: ソニーセミコンダクタソリューションズ株式会社

Inventor： 赤木　美穂 ,  安　陽太郎

IPC: H03L7/081 ,  H03K5/00 ,  H03K5/133 ,  G06F1/06 ,  G01S7/4865

Abstract: ＤＬＬ回路（１１０）は、位相遅延回路（１１４）と、選択回路（１１５）と、検出回路（１１７）と、クロック停止回路（１１６）と、を備える。位相遅延回路（１１４）は、クロック信号に応じてそれぞれ位相の異なる複数の遅延信号を生成する。選択回路（１１５）は、設定信号に応じて複数の前記遅延信号のうちの１つを出力信号として選択する。検出回路（１１７）は、前記設定信号を切り替えるタイミングを検出する。クロック停止回路（１１６）は、前記検出回路（１１７）が検出した前記タイミングを含む所定の期間、前記クロック信号の前記位相遅延回路（１１４）への入力を停止する。

公开(公告)号：WO2018057350A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/051172

申请日：2017-09-12

Applicant: ALTERA CORPORATION

Inventor： LAU, Ker Yon

IPC: H03K5/156 ,  H03K5/133

CPC classification number: H03K5/1565 ,  H03K19/21

Abstract: Duty cycle sampling circuitry is disclosed that may generate offsets that cancel each other out, thereby improving the accuracy of duty cycle sampling of input clock signals based on sampling clock signals. The input clock input signals may be swapped, or the sampling clock signals may be swapped, or both may be swapped, at various times. Erroneous samples obtained in one configuration can cancel out other erroneous samples obtained in another configuration.

Abstract translation: 公开了占空比采样电路，其可以生成彼此抵消的偏移，由此基于采样时钟信号提高输入时钟信号的占空比采样的精度。 输入时钟输入信号可以交换，或者采样时钟信号可以交换，或者两者可以在不同的时间交换。 在一种配置中获得的错误样本可以抵消其他配置中获得的其他错误样本。