公开(公告)号：WO2008122012A2

公开(公告)日：2008-10-09

申请号：PCT/US2008/059035

申请日：2008-04-01

Applicant: SANDISK CORPORATION ,  KAI, James ,  PHAM, Tuan ,  HIGASHITANI, Masaaki ,  MATAMIS, George ,  ORIMOTO, Takashi

Inventor： KAI, James ,  PHAM, Tuan ,  HIGASHITANI, Masaaki ,  MATAMIS, George ,  ORIMOTO, Takashi

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

Abstract: Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.

Abstract translation: 提供非易失性存储器和集成存储器和外围电路制造工艺。 使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。 中间电介质层设置在电荷存储区域的上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

公开(公告)号：WO2005001922A9

公开(公告)日：2007-03-22

申请号：PCT/US2004018545

申请日：2004-06-09

Applicant: SANDISK CORP ,  LUTZE JEFFREY ,  PHAM TUAN ,  CHIEN HENRY ,  MATAMIS GEORGE

Inventor： LUTZE JEFFREY ,  PHAM TUAN ,  CHIEN HENRY ,  MATAMIS GEORGE

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

Abstract: Floating gate structures (230) are disclosed that have a projection that extends away from the surface of a substrate. This projection (232, 234) may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the word line extends downwards on each side of the floating gate to shield adjacent floating gates in the same string. In another embodiment, a process for fabricating floating gates with projections is disclosed. The projection may be formed so that it is self-aligned to the rest of the floating gate.

Abstract translation: 公开了浮动栅极结构（230），其具有远离衬底的表面延伸的突起。 该突起（232,234）可以为浮动栅极提供增加的表面积，用于耦合浮动栅极和控制栅极。 在一个实施例中，字线在浮动栅极的每一侧向下延伸以屏蔽相同串中的相邻浮动栅极。 在另一个实施例中，公开了一种用于制造具有突起的浮动栅极的工艺。 突起可以形成为使得其与浮动栅极的其余部分自对准。