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    DAMASCENE METHOD OF MAKING A NONVOLATILE MEMORY DEVICE
    1.
    发明申请
    DAMASCENE METHOD OF MAKING A NONVOLATILE MEMORY DEVICE 审中-公开
    制造非易失性存储器件的DAMASCENE方法

    公开(公告)号：WO2011091416A1

    公开(公告)日：2011-07-28

    申请号：PCT/US2011/022400

    申请日：2011-01-25

    Applicant: SANDISK 3D LLC ,  PURAYATH, Vinod Robert ,  MATAMIS, George ,  KAI, James ,  ORIMOTO, Takashi

    Inventor： PURAYATH, Vinod Robert ,  MATAMIS, George ,  KAI, James ,  ORIMOTO, Takashi

    IPC: H01L27/10 ,  H01L27/102

    CPC classification number: H01L27/101 ,  H01L27/1021

    Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

    Abstract translation: 一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个 的第二轨道沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开， 所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。 第一半导体轨道沿第一方向延伸。 第二半导体轨道沿与第一方向不同的第二方向延伸。

    NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS
    3.
    发明申请
    NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS 审中-公开
    非易失性存储器，带有通道和扩展源/漏区

    公开(公告)号：WO2009129053A1

    公开(公告)日：2009-10-22

    申请号：PCT/US2009/039202

    申请日：2009-04-01

    Applicant: SANDISK CORPORATION ,  CHIEN, Henry ,  PURAYATH, Vinod, R. ,  KAI, James ,  MATAMIS, George ,  ORIMOTO, Takashi

    Inventor： CHIEN, Henry ,  PURAYATH, Vinod, R. ,  KAI, James ,  MATAMIS, George ,  ORIMOTO, Takashi

    IPC: G11C11/56 ,  G11C11/16

    CPC classification number: G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

    Abstract: A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

    Abstract translation: 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 降低。 侧壁绝缘层与底部绝缘层的厚度的比可以为约0.3〜0.67。

    METHODS OF FORMING SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES
    4.
    发明申请
    METHODS OF FORMING SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES 审中-公开
    使用辅助层形成高密度半导体器件的间隔图案的方法

    公开(公告)号：WO2008089153A3

    公开(公告)日：2008-09-12

    申请号：PCT/US2008051017

    申请日：2008-01-14

    Applicant: SANDISK CORP ,  KAI JAMES ,  METAMIS GEORGE ,  PHAM TUAN DUC ,  HIGASHITANI MASAAKI ,  ORIMOTO TAKASHI

    Inventor： KAI JAMES ,  METAMIS GEORGE ,  PHAM TUAN DUC ,  HIGASHITANI MASAAKI ,  ORIMOTO TAKASHI

    IPC: H01L21/033 ,  H01L21/28 ,  H01L21/308 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L21/28273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521

    Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers (620-634) are formed that serve as a mask, for etching one or more layers (604) beneath the spacers. An etch stop pad layer (608) having a material composition substantially similar to the spacer material is provided between a dielectric layer (606) and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

    Abstract translation: 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。 形成用作掩模的隔板（620-634），用于蚀刻间隔物下面的一个或多个层（604）。 具有与间隔物材料基本相似的材料组成的蚀刻停止衬垫层（608）设置在电介质层（606）和绝缘牺牲层（例如氮化硅）之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

    INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION
    8.
    发明申请
    INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION 审中-公开
    集成的非易失性存储器和外围电路制造

    公开(公告)号：WO2008122012A2

    公开(公告)日：2008-10-09

    申请号：PCT/US2008/059035

    申请日：2008-04-01

    Applicant: SANDISK CORPORATION ,  KAI, James ,  PHAM, Tuan ,  HIGASHITANI, Masaaki ,  MATAMIS, George ,  ORIMOTO, Takashi

    Inventor： KAI, James ,  PHAM, Tuan ,  HIGASHITANI, Masaaki ,  MATAMIS, George ,  ORIMOTO, Takashi

    IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

    CPC classification number: H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

    Abstract: Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.

    Abstract translation: 提供非易失性存储器和集成存储器和外围电路制造工艺。 使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。 中间电介质层设置在电荷存储区域的上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

    INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION
    10.
    发明申请
    INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION 审中-公开
    集成的非易失性存储器和外围电路制造

    公开(公告)号：WO2008122012A3

    公开(公告)日：2008-11-20

    申请号：PCT/US2008059035

    申请日：2008-04-01

    Applicant: SANDISK CORP ,  KAI JAMES ,  PHAM TUAN ,  HIGASHITANI MASAAKI ,  MATAMIS GEORGE ,  ORIMOTO TAKASHI

    Inventor： KAI JAMES ,  PHAM TUAN ,  HIGASHITANI MASAAKI ,  MATAMIS GEORGE ,  ORIMOTO TAKASHI

    IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

    CPC classification number: H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

    Abstract: Non-volatile memory and integrated memory (480) and peripheral circuitry (490) fabrication processes are provided. Sets of charge storage regions (406, 408), such as NAND strings including multiple non- volatile storage elements, are formed over a semiconductor substrate (402) using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer (404) is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates (416, 418) for the charge storage regions and the gate regions (434) of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions (444, 448) of these devices can be formed from the layer forming the control gates of the memory array.

    Abstract translation: 提供了非易失性存储器和集成存储器（480）和外围电路（490）制造工艺。 使用诸如第一多晶硅层的电荷存储材料层，在半导体衬底（402）上形成电荷存储区（406,408），诸如包括多个非易失性存储元件的NAND串。 中间电介质层（404）设置在电荷存储区域上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于电荷存储区域的控制栅极（416,418）和用于存储器组的选择晶体管的栅极区域（434） 元素。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域（444,448）可以由形成存储器阵列的控制栅极的层形成。

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