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    METHOD OF MANUFACTURING AIR GAP ISOLATION IN HIGH-DENSITY NON-VOLATILE MEMORY
    1.
    发明申请
    METHOD OF MANUFACTURING AIR GAP ISOLATION IN HIGH-DENSITY NON-VOLATILE MEMORY 审中-公开
    在高密度非易失性存储器中制造空气隙分离的方法

    公开(公告)号：WO2012097153A1

    公开(公告)日：2012-07-19

    申请号：PCT/US2012/021081

    申请日：2012-01-12

    Applicant: SANDISK TECHNOLOGIES, INC. ,  PACHAMUTHU, Jayavel ,  PURAYATH, Vinod, Robert ,  MATAMIS, George

    Inventor： PACHAMUTHU, Jayavel ,  PURAYATH, Vinod, Robert ,  MATAMIS, George

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/764

    CPC classification number: H01L27/11521 ,  H01L21/764 ,  H01L27/11568

    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.

    Abstract translation: 提供了非易失性存储器阵列中的气隙隔离和相关的制造工艺。 至少部分地在衬底的有源区域之间的隔离区域中形成气隙。 气隙可以在相邻层堆叠柱之间的衬底表面之上进一步延伸。 至少部分地在隔离区域中形成牺牲材料，随后形成电介质衬垫。 去除牺牲材料以在形成控制栅极层之前限定气隙，然后蚀刻它和层堆叠列以形成单独的控制栅极和列的非易失性存储元件。

    DAMASCENE METHOD OF MAKING A NONVOLATILE MEMORY DEVICE
    3.
    发明申请
    DAMASCENE METHOD OF MAKING A NONVOLATILE MEMORY DEVICE 审中-公开
    制造非易失性存储器件的DAMASCENE方法

    公开(公告)号：WO2011091416A1

    公开(公告)日：2011-07-28

    申请号：PCT/US2011/022400

    申请日：2011-01-25

    Applicant: SANDISK 3D LLC ,  PURAYATH, Vinod Robert ,  MATAMIS, George ,  KAI, James ,  ORIMOTO, Takashi

    Inventor： PURAYATH, Vinod Robert ,  MATAMIS, George ,  KAI, James ,  ORIMOTO, Takashi

    IPC: H01L27/10 ,  H01L27/102

    CPC classification number: H01L27/101 ,  H01L27/1021

    Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

    Abstract translation: 一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个 的第二轨道沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开， 所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。 第一半导体轨道沿第一方向延伸。 第二半导体轨道沿与第一方向不同的第二方向延伸。

    FLOATING GATE STRUCTURES WITH VERTICAL PROJECTIONS
    5.
    发明申请
    FLOATING GATE STRUCTURES WITH VERTICAL PROJECTIONS 审中-公开
    浮动门结构与垂直投影

    公开(公告)号：WO2005001922A1

    公开(公告)日：2005-01-06

    申请号：PCT/US2004/018545

    申请日：2004-06-09

    Applicant: SANDISK CORPORATION ,  LUTZE, Jeffrey ,  PHAM, Tuan ,  CHIEN, Henry ,  MATAMIS, George

    Inventor： LUTZE, Jeffrey ,  PHAM, Tuan ,  CHIEN, Henry ,  MATAMIS, George

    IPC: H01L29/423

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

    Abstract: Floating gate structures (230) are disclosed that have a projection that extends away from the surface of a substrate. This projection (232, 234) may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the word line extends downwards on each side of the floating gate to shield adjacent floating gates in the same string. In another embodiment, a process for fabricating floating gates with projections is disclosed. The projection may be formed so that it is self-aligned to the rest of the floating gate.

    Abstract translation: 公开了浮动栅极结构（230），其具有远离衬底的表面延伸的突起。 该突起（232,234）可以为浮动栅极提供增加的表面积，用于耦合浮动栅极和控制栅极。 在一个实施例中，字线在浮置栅极的每一侧向下延伸以屏蔽相同串中的相邻浮动栅极。 在另一个实施例中，公开了一种用于制造具有突起的浮动栅极的工艺。 突起可以形成为使得其与浮动栅极的其余部分自对准。

    NON-VOLATILE MEMORY COMPRISING BIT LINE AIR GAPS AND WORD LINE AIR GAPS AND CORRESPONDING MANUFACTURING METHOD
    6.
    发明申请
    NON-VOLATILE MEMORY COMPRISING BIT LINE AIR GAPS AND WORD LINE AIR GAPS AND CORRESPONDING MANUFACTURING METHOD 审中-公开
    非线性内存包含位线空气和字线空气GAPS和相应的制造方法

    公开(公告)号：WO2011160001A1

    公开(公告)日：2011-12-22

    申请号：PCT/US2011/040859

    申请日：2011-06-17

    Applicant: SANDISK TECHNOLOGIES, INC. ,  PURAYATH, Vinod, Robert ,  MATAMIS, George ,  HARARI, Eli ,  KINOSHITA, Hiroyuki ,  PHAM, Tuan

    Inventor： PURAYATH, Vinod, Robert ,  MATAMIS, George ,  HARARI, Eli ,  KINOSHITA, Hiroyuki ,  PHAM, Tuan

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/764

    CPC classification number: H01L21/764 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps (436) that are elongated in a column direction between the active areas. At least one cap (434) is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps (487) that are elongated in a row direction between adjacent rows of storage elements are also provided. The selective growth processes involve a modification of the surface of the charge storage regions, either by deposition of a catalyst layer or by ion implantation.

    Abstract translation: 提供了非易失性存储器阵列中的气隙隔离和相关制造工艺。 至少部分地可以通过在活动区域​​之间沿列方向延伸的位线空气间隙（436）来提供衬底的相邻有源区域之间的电隔离。 至少一个帽（434）形成在每个隔离区域上，至少部分地覆盖空气以提供相应气隙的上端点。 帽可以至少部分地沿着相邻的电荷存储区域的侧壁形成。 在各种实施方案中，选择性生长过程用于在隔离区域上形成封盖条以限定气隙。 还提供了在相邻行存储元件之间沿行方向延伸的字线气隙（487）。 选择性生长方法包括通过沉积催化剂层或通过离子注入来修饰电荷存储区域的表面。

    INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION
    8.
    发明申请
    INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION 审中-公开
    集成的非易失性存储器和外围电路制造

    公开(公告)号：WO2008122012A3

    公开(公告)日：2008-11-20

    申请号：PCT/US2008059035

    申请日：2008-04-01

    Applicant: SANDISK CORP ,  KAI JAMES ,  PHAM TUAN ,  HIGASHITANI MASAAKI ,  MATAMIS GEORGE ,  ORIMOTO TAKASHI

    Inventor： KAI JAMES ,  PHAM TUAN ,  HIGASHITANI MASAAKI ,  MATAMIS GEORGE ,  ORIMOTO TAKASHI

    IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

    CPC classification number: H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

    Abstract: Non-volatile memory and integrated memory (480) and peripheral circuitry (490) fabrication processes are provided. Sets of charge storage regions (406, 408), such as NAND strings including multiple non- volatile storage elements, are formed over a semiconductor substrate (402) using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer (404) is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates (416, 418) for the charge storage regions and the gate regions (434) of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions (444, 448) of these devices can be formed from the layer forming the control gates of the memory array.

    Abstract translation: 提供了非易失性存储器和集成存储器（480）和外围电路（490）制造工艺。 使用诸如第一多晶硅层的电荷存储材料层，在半导体衬底（402）上形成电荷存储区（406,408），诸如包括多个非易失性存储元件的NAND串。 中间电介质层（404）设置在电荷存储区域上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于电荷存储区域的控制栅极（416,418）和用于存储器组的选择晶体管的栅极区域（434） 元素。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域（444,448）可以由形成存储器阵列的控制栅极的层形成。

    NAND MEMORY WITH DUAL CONTROL GATES HAVING FIXED CHARGE LAYER BELOW CONTROL GATES
    9.
    发明申请
    NAND MEMORY WITH DUAL CONTROL GATES HAVING FIXED CHARGE LAYER BELOW CONTROL GATES 审中-公开
    具有双控制门的NAND存储器具有下面的固定充电层下面的控制门

    公开(公告)号：WO2008088654A1

    公开(公告)日：2008-07-24

    申请号：PCT/US2007/088145

    申请日：2007-12-19

    Applicant: SANDISK CORPORATION ,  CHIEN, Henry ,  MATAMIS, George ,  ORIMOTO, Takashi ,  KAI, James

    Inventor： CHIEN, Henry ,  MATAMIS, George ,  ORIMOTO, Takashi ,  KAI, James

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51

    CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825

    Abstract: A string (200) of nonvolatile memory cells are connected together by source/drain regions (202-205)- that include an inversion layer created by fixed charge in an overlying layer (210-213). Control gates (220-223) extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation. Fixed charges may also be located between floating gates and the underlying substrate surface. Fixed charge over source/drain regions and under floating gates are formed together in a common deposition.

    Abstract translation: 非易失性存储单元的串（200）由源/漏区（202-205）连接在一起，包括在上层（210-213）中由固定电荷产生的反型层。 控制栅极（220-223）在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。 可以通过等离子体氮化形成固定电荷层。 固定电荷也可以位于浮动栅极和下面的衬底表面之间。 源极/漏极区域和浮置栅极之间的固定电荷一起形成在共同的沉积中。

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