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    METHOD AND STRUCTURE FOR SOLVING THE EVIL-TWIN PROBLEM
    23.
    发明申请
    METHOD AND STRUCTURE FOR SOLVING THE EVIL-TWIN PROBLEM 审中-公开
    求解双胞胎问题的方法和结构

    公开(公告)号：WO2010123541A3

    公开(公告)日：2010-12-16

    申请号：PCT/US2010001099

    申请日：2010-04-13

    Applicant: ORACLE AMERICA INC FORMERLY KNOWN AS SUN MICROSYSTEMS INC

    Inventor： CHAUDHRY SHAILENDER ,  TREMBLAY MARC

    IPC: G06F9/30

    CPC classification number: G06F9/30098 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3838 ,  G06F9/384

    Abstract: A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.

    Abstract translation: 处理器中的寄存器文件包括第一大小的第一多个寄存器，n位。 解码器使用将寄存器文件划分成具有第二大小的第二M个寄存器的映射。 每个具有第二大小的寄存器在连续名称空间中被分配不同的名称。 第二大小的每个寄存器包括具有第一大小的多个N个寄存器，n位。 多个N个寄存器中的每个寄存器被分配与包括该多个的第二大小的寄存器相同的名称。 状态信息保存在每个n位寄存器的寄存器文件中。 通过连续名称空间检测指令对其他指令的依赖性。 状态信息允许处理器确定寄存器的任何部分或全部中的信息何时有效。

    METHOD AND STRUCTURE FOR SOLVING THE EVIL-TWIN PROBLEM
    24.
    发明申请
    METHOD AND STRUCTURE FOR SOLVING THE EVIL-TWIN PROBLEM 审中-公开
    解决双向问题的方法与结构

    公开(公告)号：WO2010123541A2

    公开(公告)日：2010-10-28

    申请号：PCT/US2010/001099

    申请日：2010-04-13

    Applicant: ORACLE AMERICA, INC. formerly known as SUN MICROSYSTEMS, INC.

    Inventor： CHAUDHRY, Shailender ,  TREMBLAY, Marc

    IPC: G06F9/30

    CPC classification number: G06F9/30098 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3838 ,  G06F9/384

    Abstract: A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.

    Abstract translation: 在处理器中的寄存器文件包括第一大小的n位的第一多个寄存器。 解码器使用将寄存器文件分成具有第二大小的第二多个寄存器M的映射。 具有第二大小的每个寄存器在连续的名称空间中被分配不同的名称。 第二大小的每个寄存器包括多个N个第一大小的寄存器，n位。 多个N个寄存器中的每个寄存器被分配与包括该多个寄存器的第二大小的寄存器相同的名称。 状态信息保存在每个n位寄存器的寄存器文件中。 通过连续的名称空间检测指令对其他指令的依赖性。 状态信息允许处理器确定寄存器的任何部分或全部中的信息何时有效。

    MICROCONTROLLER WITH SPECIAL BANKING INSTRUCTIONS
    26.
    发明申请
    MICROCONTROLLER WITH SPECIAL BANKING INSTRUCTIONS 审中-公开
    具有特殊银行指示的微控制器

    公开(公告)号：WO2010093661A2

    公开(公告)日：2010-08-19

    申请号：PCT/US2010/023706

    申请日：2010-02-10

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  LUNDSTRUM, Zeke, R. ,  DELPORT, Vivien ,  STEEDMAN, Sean ,  JULICHER, Joseph

    Inventor： LUNDSTRUM, Zeke, R. ,  DELPORT, Vivien ,  STEEDMAN, Sean ,  JULICHER, Joseph

    IPC: G06F9/30

    CPC classification number: G06F9/3012 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/342 ,  G06F9/35 ,  G06F12/0623

    Abstract: An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.

    Abstract translation: 一种用于具有划分成多个存储体的数据存储器的微控制器的指令集，其中数据存储器具有多个存储体的多于一个存储体，其形成没有特殊功能寄存器映射的线性数据存储器块， 没有映射到用于选择存储体的数据存储器并且映射到至少一个存储体的间接访问寄存器的存储体选择寄存器，其中指令集包括可以直接寻址一个存储体内的所有存储器位置的多个指令 至少一个提供对存储体选择寄存器的访问的指令，以及使用间接访问寄存器向数据存储器执行间接地址的至少一个指令。

    SYSTEM AND METHOD OF INDIRECT REGISTER ACCESS
    27.
    发明申请
    SYSTEM AND METHOD OF INDIRECT REGISTER ACCESS 审中-公开
    间接注册访问的系统和方法

    公开(公告)号：WO2010045028A1

    公开(公告)日：2010-04-22

    申请号：PCT/US2009/059128

    申请日：2009-09-30

    Applicant: MICRON TECHNOLOGY, INC. ,  NOYES, Harold B. ,  JURENKA, Mark ,  HUGGINS, Gavin

    Inventor： NOYES, Harold B. ,  JURENKA, Mark ,  HUGGINS, Gavin

    IPC: G06F9/30 ,  G06F9/318

    CPC classification number: G06F9/35 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34

    Abstract: Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address.

    Abstract translation: 提供了系统和方法来管理对寄存器的访问。 系统可以包括一组直接寄存器和一组间接寄存器。 间接寄存器可以通过直接寄存器访问，直接寄存器可以提供各种功能，以便更快地访问间接寄存器。 直接寄存器之一可能指示访问间接寄存器的访问模式。 访问模式可以包括自动递增，自动递减，自动复位，无改变模式。 基于访问模式，可以在访问地址上的间接寄存器后自动修改当前访问的地址。

    METHOD AND INSTRUCTION SET INCLUDING REGISTER SHIFTS AND ROTATES FOR DATA PROCESSING
    28.
    发明申请
    METHOD AND INSTRUCTION SET INCLUDING REGISTER SHIFTS AND ROTATES FOR DATA PROCESSING 审中-公开
    包括用于数据处理的寄存器移位和转移的方法和指令集

    公开(公告)号：WO2009073787A1

    公开(公告)日：2009-06-11

    申请号：PCT/US2008/085539

    申请日：2008-12-04

    Applicant: SANDBRIDGE TECHNOLOGIES, INC.

    Inventor： MOUDGILL, Mayan

    IPC: G06F7/38

    CPC classification number: G06F9/30098 ,  G06F9/30032 ,  G06F9/30036

    Abstract: A method includes identifying a first register with M bits and a second register with N bits. The process also includes shifting K bits, where K

    Abstract translation: 一种方法包括用M位识别第一寄存器和用N位的第二寄存器。 该过程还包括将K位从第二寄存器移位到第一寄存器中，其中K <= N。 移位操作执行包括从第一寄存器读取位K ... N-1的左移操作，将位K ... N-1写入第一寄存器的位位置O ... NK-1，读取K位 将第二寄存器的K位写入第一寄存器的位置NK ... N-1或包含从第一寄存器读取位O ... NK-1的右移操作，写入位O. ..NK-1进入第一个寄存器的位位置K ... N-1，从第二个寄存器读取K位，并将第二个寄存器的K位写入第一个寄存器的位位置0 ... K-1。

    PARALLEL ARCHITECTURE FOR MATRIX TRANSPOSITION
    29.
    发明申请
    PARALLEL ARCHITECTURE FOR MATRIX TRANSPOSITION 审中-公开
    矩阵变换的并行结构

    公开(公告)号：WO2008103885A3

    公开(公告)日：2008-10-16

    申请号：PCT/US2008054685

    申请日：2008-02-22

    Applicant: TEXAS INSTRUMENTS INC ,  WON NARA ,  HUNG CHING-YU

    Inventor： WON NARA ,  HUNG CHING-YU

    IPC: G06F9/26 ,  G06F9/34 ,  G06F12/00

    CPC classification number: G06F17/18 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098

    Abstract: An extension to current multiple memory bank (309) video processing architecture is presented. A more powerful memory controller (310, 311) is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths (316) making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.

    Abstract translation: 介绍了当前多存储体（309）视频处理体系结构的扩展。 结合更强大的存储器控​​制器（310,311），允许在输入和输出数据路径（316）处计算多个存储器地址，使得可能在输入和输出端口处进行读取和写入的新组合。 用于图像和视频处理的算法所需的矩阵转置计算在MAC模块和存储体中实现。 这里描述的技术可以应用于其他并行处理器，包括未来的VLIW DSP处理器。

    PARALLEL ARCHITECTURE FOR MATRIX TRANSPOSITION
    30.
    发明申请
    PARALLEL ARCHITECTURE FOR MATRIX TRANSPOSITION 审中-公开
    矩阵运输的平行建筑

    公开(公告)号：WO2008103885A2

    公开(公告)日：2008-08-28

    申请号：PCT/US2008/054685

    申请日：2008-02-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  WON, Nara ,  HUNG, Ching-Yu

    Inventor： WON, Nara ,  HUNG, Ching-Yu

    IPC: G06F17/14

    CPC classification number: G06F17/18 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098

    Abstract: An extension to current multiple memory bank (309) video processing architecture is presented. A more powerful memory controller (310, 311) is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths (316) making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.

    Abstract translation: 介绍了当前多存储器（309）视频处理架构的扩展。 结合了更强大的存储器控​​制器（310,311），允许在输入和输出数据路径（316）处计算多个存储器地址，使得在输入和输出端口处的读取和写入成为新的组合。 在图像和视频处理中使用的算法所需的矩阵转置计算在MAC模块和存储器中实现。 这里描述的技术可以应用于其他并行处理器，包括将来的VLIW DSP处理器。

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