公开(公告)号：WO2004093327A3

公开(公告)日：2005-12-29

申请号：PCT/US2004010765

申请日：2004-04-07

Applicant: SILICON LAB INC ,  KHOINI-POORFARD RAMIN ,  KRONE ANDREW W

Inventor： KHOINI-POORFARD RAMIN ,  KRONE ANDREW W

IPC: H03D3/00 ,  H03L7/18 ,  H04N5/50 ,  H04N7/20

CPC classification number: H04N5/4446 ,  H03D3/006 ,  H03D3/007 ,  H03L7/18 ,  H04H40/90 ,  H04N5/4401 ,  H04N5/50 ,  H04N7/20 ,  H04N21/4263

Abstract: Receiver architectures and associated methods are disclosed that provide initial analog coarse tuning (102) of desired channels (108) within a received signal spectrum (107), such as a set-top box signal spectrum for satellite communications. These architectures provide significant advantages over prior direct down-conversion (DDC) architectures and low intermediate-frequency (IF) architectures, particularly where two tuners are desired on the same integrated circuit. Rather than using a low-IF frequency or directly converting the desired channel frequency to DC, initial coarse tuning provided by analog coarse tuning circuitry (102) allows for a conversion to a frequency range around DC. This coarse tuning circuitry can be implemented, for example, using a large-step local oscillator (LO) (106) that provides a coarse tune analog mixing signal (116). Once mixed down, the desired channel may then be fine-tuned through digital processing (104), such as through the use of a wide-band analog-to-digital converter (ADC) or a narrow-band tunable bandpass ADC.

Abstract translation: 公开了提供接收信号频谱（107）内的期望信道（108）的初始模拟粗略调谐（102）的接收机架构和相关方法，例如用于卫星通信的机顶盒信号频谱。 这些架构与先前的直接下变频（DDC）架构和低中频（IF）架构相比具有显着的优势，特别是在同一集成电路上需要两个调谐器的情况下。 不是使用低IF频率或直接将期望的信道频率转换为DC，由模拟粗调谐电路（102）提供的初始粗调调允许转换到DC周围的频率范围。 该粗调谐电路可以例如使用提供粗调模拟混合信号（116）的大步本地振荡器（LO）（106）来实现。 一旦混合，则可以通过数字处理（104），例如通过使用宽带模数转换器（ADC）或窄带可调谐带通ADC来微调所需的信道。

公开(公告)号：WO2004079924A3

公开(公告)日：2005-10-27

申请号：PCT/US2004005213

申请日：2004-02-23

Applicant: SILICON LAB INC ,  JOHNSON RICHARD A

Inventor： JOHNSON RICHARD A

IPC: H03C3/40 ,  H03D7/14 ,  H03D7/16 ,  H04B1/18 ,  H04L27/06

CPC classification number: H03D7/1441 ,  H03C3/403 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/166 ,  H03D2200/0043 ,  H03D2200/0047 ,  H03D2200/009

Abstract: A tuner architecture (100) is disclosed that mixes an analog RF input signal (302) and a digital local oscillator signal (306) to generate a output signal (304) at a desired IF frequency, including low-IF and zero-IF solutions. The tuner provides a number of advantages over previous implementations, such as improved performance for low-IF and zero-IF architectures and a significant reduction in interference between adjacent paths in a multiple tuner solution. Other features and variations can be implemented, if desired, and related methods can be utilized, as well.

Abstract translation: 公开了一种调谐器架构（100），其混合模拟RF输入信号（302）和数字本地振荡器信号（306）以产生期望的IF频率的输出信号（304），包括低IF和零中频解 。 调谐器提供了许多优于先前实现的优点，例如用于低中频和零中频架构的改进的性能以及在多调谐器解决方案中相邻路径之间的干扰的显着降低。 如果需要，可以实现其它特征和变化，并且也可以使用相关方法。

公开(公告)号：WO2009006193A3

公开(公告)日：2009-02-26

申请号：PCT/US2008068326

申请日：2008-06-26

Applicant: SILICON LAB INC ,  PIOVACCARI ALESSANDRO ,  NOAKES GEOFFREY B ,  THOMPSON DANIEL M

Inventor： PIOVACCARI ALESSANDRO ,  NOAKES GEOFFREY B ,  THOMPSON DANIEL M

IPC: H01Q1/24

CPC classification number: H04B1/3877

Abstract: In one embodiment, the present invention includes an accessory device for coupling to a portable system having an AM radio receiver. The accessory device includes a housing to house at least one accessory component and an AM antenna.

Abstract translation: 在一个实施例中，本发明包括用于耦合到具有AM无线电接收机的便携式系统的附件装置。 附件装置包括容纳至少一个辅助部件和AM天线的壳体。

公开(公告)号：WO2009015146A2

公开(公告)日：2009-01-29

申请号：PCT/US2008070765

申请日：2008-07-22

Applicant: SILICON LAB INC ,  TAIPALE DANA ,  CHAMPAGNE GERALD

Inventor： TAIPALE DANA ,  CHAMPAGNE GERALD

IPC: H04H40/18

CPC classification number: H04H40/18 ,  H04H60/11 ,  H04H2201/13 ,  H04L1/0045

Abstract: A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

Abstract translation: 一种接收机，包括第一电路，其被配置为组合来自作为广播信道的一部分传输的至少两组RDS / RBDS数据的相应软判决值，以生成一组组合值，以及第二电路，其被配置为识别指示的组合值的子集 提供了来自RDS / RBDS数据的至少两组的接收值的相对恒定的子集。

公开(公告)号：WO2007101178A3

公开(公告)日：2009-01-22

申请号：PCT/US2007062850

申请日：2007-02-27

Applicant: SILICON LAB INC ,  MARQUES AUGUSTO

Inventor： MARQUES AUGUSTO

IPC: G01R23/00

CPC classification number: H03L7/00 ,  H03L1/022 ,  H03L7/183

Abstract: A programmable reference-less oscillator provides a wide range of programmable output frequencies. The programmable reference-less oscillator is implemented on an integrated circuit that includes a free running controllable oscillator circuit such as a voltage controlled oscillator (VCO), a programmable divider circuit coupled to divide an output of the controllable oscillator circuit according to a programmable divide value. A non-volatile storage stores the programmed divide value and a control word that controls the output of the controllable oscillator circuit. The control word provides a calibration capability to achieve a desired output frequency in conjunction with the programmable divider circuit. Open loop temperature compensation is achieved by adjusting the control word according to a temperature detected by a temperature sensor on the integrated circuit. Additional clock accuracy may be achieved by adjusting the control word for process as well as temperature.

Abstract translation: 可编程的无参考振荡器提供了广泛的可编程输出频率。 可编程基准无源振荡器在集成电路上实现，该集成电路包括自由运行的可控振荡器电路，例如压控振荡器（VCO），可编程分频器电路，其被耦合以根据可编程分频值对可控振荡器电路的输出进行分频 。 非易失性存储器存储编程的分频值和控制可控振荡器电路的输出的控制字。 控制字提供校准功能，以结合可编程分频器电路实现所需的输出频率。 通过根据由集成电路上的温度传感器检测到的温度调节控制字来实现开环温度补偿。 可以通过调整过程控制字和温度来实现额外的时钟精度。

公开(公告)号：WO2008042134A3

公开(公告)日：2008-11-20

申请号：PCT/US2007020564

申请日：2007-09-21

Applicant: SILICON LAB INC ,  TAIPALE DANA ,  ELENES JAVAIER

Inventor： TAIPALE DANA ,  ELENES JAVAIER

IPC: H03D1/00

CPC classification number: H03D1/2245

Abstract: In one aspect, the present invention includes a method for receiving an amplitude modulation (AM) signal in a receiver and performing a coordinate rotation digital computer (CORDIC) operation in obtaining a demodulated AM signal. The demodulated AM signal may be obtained from a magnitude output of the CORDIC operation or as a real output of a multiplication between a complex baseband signal and a demodulating carrier signal generated in a feedback loop.

Abstract translation: 在一个方面，本发明包括一种用于在接收机中接收幅度调制（AM）信号并且执行坐标旋转数字计算机（CORDIC）操作以获得解调的AM信号的方法。 解调后的AM信号可以从CORDIC操作的幅度输出中获得，或者作为在反馈回路中生成的复基带信号和解调载波信号之间的乘法的实际输出。

公开(公告)号：WO2007127015A2

公开(公告)日：2007-11-08

申请号：PCT/US2007007860

申请日：2007-03-29

Applicant: SILICON LAB INC ,  DER LAWRENCE ,  TUTTLE GEORGE T ,  PIOVACCARI ALESSANDRO ,  XIN CHUNYU ,  HABAN SCOTT ,  ELENES JAVIER ,  KASHA DAN ,  VANCORENLAND PETER

Inventor： DER LAWRENCE ,  TUTTLE GEORGE T ,  PIOVACCARI ALESSANDRO ,  XIN CHUNYU ,  HABAN SCOTT ,  ELENES JAVIER ,  KASHA DAN ,  VANCORENLAND PETER

IPC: H04B1/40

CPC classification number: H04B1/40 ,  H03M3/398 ,  H03M3/40 ,  H03M3/448 ,  H03M3/452 ,  H03M3/50

Abstract: A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.

Abstract translation: 收发器包括处理器和模数转换器。 处理器适于在收发器的发射模式中，响应于第一数字信号产生调制信号。 在收发器的接收模式中，处理器适于响应于第二数字信号产生解调信号。 模数转换器以发送模式提供第一数字信号，并在接收模式下提供第二数字信号。

公开(公告)号：WO2006105185A3

公开(公告)日：2007-05-18

申请号：PCT/US2006011447

申请日：2006-03-29

Applicant: SILICON LAB INC ,  OUZILLOU MENDY M

Inventor： OUZILLOU MENDY M

IPC: H04B1/38 ,  H01Q1/24

CPC classification number: H04B1/0057 ,  H01Q1/242 ,  H04B1/005 ,  H04B1/006 ,  H04B1/0064

Abstract: A method and apparatus is provided for partitioning a radio (10, 20, 30, 40, 50, 60, 80) using a multi-chip module (12, 22, 32, 42, 52, 62, 82) to group some or all of the components of the radio in a single package. In one example, a radio uses a multi-chip module, including a chip carrier (14). Various components of the radio reside in integrated circuits that are mounted to the chip carrier (14). If desired, one or more antennas (22) can be integrated into the chip carrier (14).

Abstract translation: 提供一种方法和装置，用于使用多芯片模块（12,22,32,42,52,62,82）来划分无线电装置（10,20,30,40,50,60,80）以将一些或多个 无线电的所有组件在单个包中。 在一个示例中，无线电使用包括芯片载体（14）的多芯片模块。 无线电的各种组件驻留在安装到芯片载体（14）的集成电路中。 如果需要，一个或多个天线（22）可以集成到芯片载体（14）中。

公开(公告)号：WO2007018888A2

公开(公告)日：2007-02-15

申请号：PCT/US2006026700

申请日：2006-07-11

Applicant: SILICON LAB INC

Inventor： JOHNSON RICHARD A ,  NOHRDEN JAMES M ,  DUPUIE SCOTT T ,  DORNBUSCH ANDREW W

IPC: H03J1/00 ,  H03D7/00 ,  H04B1/06 ,  H04B1/18 ,  H04B1/28 ,  H04B7/00 ,  H04B15/04

CPC classification number: H03J1/0008 ,  H03D7/00 ,  H04B1/0007 ,  H04B1/28 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/065 ,  H04N5/4446 ,  H04N5/46 ,  H04N21/4263 ,  H04N21/4305

Abstract: A receiver (1100) includes a direct digital frequency synthesizer (130), a mixer (105), and a clock source (1110, 1130). The direct digital frequency synthesizer has an input terminal for receiving a first clock signal at a first frequency, and an output terminal for providing a digital local oscillator signal synchronously with the first clock signal. The mixer (105) has a first input terminal for receiving a radio frequency (RF) signal, a second input terminal coupled to the output terminal of the direct digital frequency synthesizer (130), and an output terminal for providing an IF signal having a spectrum centered about a selectable one of a plurality of center frequencies. The clock source (1110, 1130) has an output terminal for providing the first clock signal without using any harmonic frequency that overlaps the spectrum for any of the plurality of center frequencies.

Abstract translation: 接收器（1100）包括直接数字频率合成器（130），混频器（105）和时钟源（1110,1130）。 直接数字频率合成器具有用于以第一频率接收第一时钟信号的输入端子和用于与第一时钟信号同步地提供数字本地振荡器信号的输出端子。 混频器（105）具有用于接收射频（RF）信号的第一输入端，耦合到直接数字频率合成器（130）的输出端的第二输入端，以及用于提供IF信号的输出端， 频谱以多个中心频率中的可选择的一个为中心。 时钟源（1110,1130）具有用于提供第一时钟信号的输出端，而不使用与多个中心频率中的任何一个的频谱重叠的任何谐波频率。

公开(公告)号：WO2004036654A3

公开(公告)日：2004-07-01

申请号：PCT/US0332649

申请日：2003-10-15

Applicant: SILICON LAB INC

Inventor： WEI DERRICK C ,  SHI YING ,  SMITH KEVIN G ,  PROFFITT STEVEN P ,  THOMSEN AXEL ,  PIETRUSZYNSKI DAVID M ,  ZHANG LIGANG

IPC: H01L23/552 ,  H01L23/64 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01F2017/008 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/0401

Abstract: An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formedaround the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.

Abstract translation: 可以在多层封装衬底（MLS）内制造电磁屏蔽的高Q电感器。 电感器优选构造为MLS层上的环路结构，并且围绕电感器形成屏蔽结构，以将电感器基本上包围在法拉第笼状壳体中。 屏蔽结构包括在MLS的另一层上形成在电感器上方的顶板，以及形成在MLS的另一层上的底板或集成电路管芯的下面并连接到MLS上的层，优选地使用 焊锡凸块 屏蔽结构侧壁可以由堆叠的通孔环或通孔形成。 电感器优选地连接到堆叠的通孔，其通过附加的焊料凸块和穿过屏蔽结构的底板的切口提供到下面的集成电路管芯的连接。