公开(公告)号：WO2004021352A1

公开(公告)日：2004-03-11

申请号：PCT/US2003/026641

申请日：2003-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KEETH, Brent ,  JOHNSON, Brian ,  LIN, Feng

IPC: G11C7/10

CPC classification number: G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C11/4076 ,  G11C2207/2281

Abstract: An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock (129) is produced from the external clock signal (116) in a delay lock loop circuit (120) and a start signal (118), produced in response to a read command (112), is passed through a delay circuit (132) slaved with the delay lock loop (120) so that the read clock signal (129) and a delayed start signal (174) are subject to the same internal timing variations. The delayed start signal (174) is used to thereby control the output of read data by the read clock signal (129).

Abstract translation: 一种用于协调从外部时钟信号导出的内部时钟信号的可变定时的装置和方法，以确保读取数据和用于锁存读取数据的读取时钟同步并以指定的读取延迟到达数据锁存器。 在延迟锁定环电路（120）中，从外部时钟信号（116）产生读时钟（129），响应于读命令（112）产生的起始信号（118）通过延迟电路 （132），其被延迟锁定环（120）从动，使得读取时钟信号（129）和延迟启动信号（174）受到相同的内部时序变化。 延迟启动信号（174）用于通过读时钟信号（129）控制读数据的输出。

公开(公告)号：WO2003058630A1

公开(公告)日：2003-07-17

申请号：PCT/US2002/040447

申请日：2002-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JOHNSON, Brian ,  KEETH, Brent ,  JANZEN, Jeffrey W. ,  MANNING, Troy A. ,  MARTIN, Chris G.

IPC: G11C7/22

CPC classification number: G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clcking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

Abstract translation: 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路被耦合到时钟输入端，并且在正常操作模式下响应于外部时钟信号响应于在设备中产生至少一个内部时钟信号控制电路，响应于预定的 施加到设备的异步输入端子的异步信号的顺序，以将设备置于其中禁用内部打包电路的替代操作模式，使得可以使用具有频率较小的外部时钟信号在替代模式下操作该设备 比预定的最小频率。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

公开(公告)号：WO2003021455A1

公开(公告)日：2003-03-13

申请号：PCT/US2002/025835

申请日：2002-08-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BAKER, R., Jacob ,  KEETH, Brent

IPC: G06F13/16

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/287 ,  G06F13/4234 ,  G11C11/42 ,  H04B10/802 ,  H04L12/40013 ,  H04Q11/0071 ,  Y02D10/14 ,  Y02D10/151

Abstract: An optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.

Abstract translation: 公开了一种用于实现控制器和存储器件之间的电气隔离的光学链路。 光链路增加了电互连的抗噪声能力，并且允许存储器件被放置在距离处理器更远的位置，而不需要耗电的I / O缓冲器。

公开(公告)号：WO1997028532A1

公开(公告)日：1997-08-07

申请号：PCT/US1997001569

申请日：1997-01-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  KEETH, Brent

IPC: G11C11/409

CPC classification number: G11C7/18 ,  G11C11/4097

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract translation: 描述了一种新颖的双层DRAM架构，其在保持传统折叠架构的噪声性能的同时实现了裸片尺寸的显着降低。 芯片尺寸的减小主要是通过以一种交叉点存储单元布局构建具有6F 2或更小的存储单元的存储器阵列。 存储器阵列利用堆叠数字线和垂直数字线扭转来实现折叠架构操作和噪声性能。

公开(公告)号：WO2022164507A1

公开(公告)日：2022-08-04

申请号：PCT/US2021/061354

申请日：2021-12-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BREWER, Tony M. ,  KEETH, Brent

IPC: G11C29/52 ,  G11C29/42 ,  G06F11/10

Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.

公开(公告)号：WO2021126496A1

公开(公告)日：2021-06-24

申请号：PCT/US2020/062034

申请日：2020-11-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JOHNSON, James, Brian ,  KEETH, Brent

IPC: G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for latency offset for frame-based communications are described. A memory system may include a host device and a memory device that communicate using frames based on a frame period of a frame clock. The memory device may receive a read command and a write command from the host device, and determine a read latency and a write latency corresponding to the received commands. The memory device may also determine an additional offset latency to add to the write latency to avoid bus contention between read data and write data associated with the read command and the write command, respectively. The offset latency may correspond to an integer quantity of clock periods, which may be less than the frame period.

公开(公告)号：WO2020061318A1

公开(公告)日：2020-03-26

申请号：PCT/US2019/051942

申请日：2019-09-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KEETH, Brent

IPC: G11C5/04 ,  G11C5/06 ,  G11C11/402

Abstract: Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. the multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.

公开(公告)号：WO2018231423A1

公开(公告)日：2018-12-20

申请号：PCT/US2018/033317

申请日：2018-05-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KEETH, Brent

IPC: G11C11/4096 ,  G11C5/06 ,  G11C8/12

Abstract: Systems, apparatuses, and methods related to dynamic random access memory (DRAM), such as finer grain DRAM, are described. For example, an array of memory cells in a memory device may be partitioned into regions. Each region may include a plurality of banks of memory cells. Each region may be associated with a data channel configured to communicate with a host device. In some examples, each channel of the array may include two or more data pins. The ratio of data pins per channel may be two or four in various examples. Other examples may include eight data pins per channel.

公开(公告)号：WO2018044456A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/044638

申请日：2017-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YANG, Gloria ,  MATHEW, Suraj J. ,  SINGANAMALLA, Raghunath ,  NAIR, Vinay ,  DERNER, Scott, J. ,  SHORE, Michael, Amiel ,  KEETH, Brent ,  SIMSEK-EGE, Fatma Arzum ,  TRAN, Diem Thy N.

IPC: H01L27/108

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract translation: 一些实施例包括具有第一和第二晶体管的存储器单元以及相对于第一和第二晶体管垂直移位的电容器。 电容器具有与第一晶体管的源极/漏极区电耦合的第一节点，与第二晶体管的源极/漏极区电耦合的第二节点以及第一节点和第二节点之间的电容器电介质材料。 一些实施例包括具有相对于彼此垂直移位的第一和第二晶体管的存储器单元，以及在第一和第二晶体管之间的电容器。 电容器具有与第一晶体管的源极/漏极区域电耦合的第一节点，与第二晶体管的源极/漏极区域电耦合的第二节点以及第一节点和第二节点之间的电容器电介质材料。

公开(公告)号：WO2014149851A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/021211

申请日：2014-03-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEDDELOH, Joe M. ,  KEETH, Brent

IPC: H01L23/50

CPC classification number: G11C5/066 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4063 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

Abstract translation: 本文一般地描述了用于提供柔性存储器系统的系统和方法的实施例。 在一些实施例中，提供了衬底，其中存储器堆叠耦合到衬底。 内存堆包括多个保管库。 控制器还耦合到基板并且包括耦合到存储器堆栈的多个保管库的多个保管库接口块，其中保管库接口块的数量小于保管库的数量。