公开(公告)号：WO2017044338A1

公开(公告)日：2017-03-16

申请号：PCT/US2016/049286

申请日：2016-08-29

申请人： CYPRESS SEMICONDUCTOR CORPORATION

发明人： AGRAWAL, Vineet ,  BETTMAN, Roger ,  LESHNER, Samuel

IPC分类号： G06F12/02 ,  G11C11/21 ,  G11C11/34 ,  G11C16/02 ,  G11C16/04

CPC分类号： G11C7/18 ,  G06F12/023 ,  G06F2212/1044 ,  G11C5/147 ,  G11C7/06 ,  G11C7/1015 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

摘要： Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line.. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.

摘要翻译： 这里公开了用于并行读写操作的系统，方法和装置。 设备可以包括耦合到本地位线的第一传输设备和与存储器阵列的存储器单元相关联的全局位线。 第一传输设备可以被配置为选择性地将全局位线耦合到本地位线。设备还可以包括耦合到本地位线的第一设备和读出放大器。 第一器件可以被配置为选择性地将局部位线耦合到读出放大器。 该装置还可以包括耦合到本地位线和电接地的第二装置。 第二装置可以被配置为选择性地将局部位线耦合到电接地。

公开(公告)号：WO2014191838A2

公开(公告)日：2014-12-04

申请号：PCT/IB2014/001772

申请日：2014-05-15

申请人： MARVELL WORLD TRADE LTD.

发明人： ZHU, Jun ,  CAO, Joseph, Jun ,  CHEN, Shawn

CPC分类号： G06F13/1689 ,  G11C7/02 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2207/2281

摘要： Systems and methods for timing read operations with a memory device are provided. A timing signal from the memory device is received at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating circuit is configured to open the gating window based on a control signal. The gating circuit is further configured to close the gating window based on a first edge of the timing signal. The first edge is determined based on a counter that is triggered to begin counting by the control signal. At a timing control circuit, the control signal is generated based on i) a count signal from the counter, and ii) a second edge of the timing signal that precedes the first edge in time.

摘要翻译： 提供了使用存储器件定时读取操作的系统和方法。 来自存储装置的定时信号在选通电路处被接收。 定时信号在门控窗口期间作为滤波的定时信号通过。 门控电路被配置为基于控制信号打开门控窗口。 门控电路还被配置为基于定时信号的第一边缘闭合门控窗口。 第一边缘是基于被触发开始计数的计数器确定的。 在定时控制电路中，基于i）来自计数器的计数信号，以及ii）在时间上先于第一边缘的定时信号的第二边缘产生控制信号。

公开(公告)号：WO2009048486A1

公开(公告)日：2009-04-16

申请号：PCT/US2008/004439

申请日：2008-04-04

申请人： MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat ,  SU, Jason, T. ,  CHEN, Hong-Yi ,  SHEU, Jason ,  TJENG, Jensen

发明人： SUTARDJA, Sehat ,  SU, Jason, T. ,  CHEN, Hong-Yi ,  SHEU, Jason ,  TJENG, Jensen

IPC分类号： G06F12/08 ,  G11C7/12 ,  G06F9/38

CPC分类号： G06F12/0882 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3804 ,  G06F9/3844 ,  G11C7/06 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/2245 ,  G11C2207/2281 ,  Y02D10/13

摘要： A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.

摘要翻译： 处理器包括具有阵列，字线和位线的高速缓冲存储器。 控制模块在访问周期期间访问阵列的单元以访问存储在高速缓冲存储器中的指令。 控制模块执行第一离散读取和第一顺序读取之一以访问连接到第一字线的阵列的第一组单元中的指令，并且选择性地执行第二离散读取和第二顺序读取之一 在分支指令上访问连接到第二字线的阵列的第二组单元格中的指令。 第二个字线与第一个字线不同。

公开(公告)号：WO2007111709A3

公开(公告)日：2008-03-27

申请号：PCT/US2006061044

申请日：2006-11-17

申请人： QUALCOMM INC ,  JUNG CHANG HO

发明人： JUNG CHANG HO

IPC分类号： G11C7/10 ,  G11C7/22

CPC分类号： G11C7/22 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/16 ,  G11C2207/108 ,  G11C2207/2281 ,  G11C2207/229

摘要： A pseudo-dual port memory (1) has a first port, a second port, and an array of six-transistor memory cells (19). A first memory access is initiated upon a rising edge of a first clock signal (ACLK) received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal (BCLK) received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.

摘要翻译： 伪双端口存储器（1）具有第一端口，第二端口和六晶体管存储单元（19）的阵列。 在接收到第一端口的第一时钟信号（ACLK）的上升沿开始第一存储器访问。 响应于接收到第二端口的第二时钟信号（BCLK）的上升沿来启动第二存储器访问。 如果第二时钟信号的上升沿在第一时间段内发生，则在伪双端口方式完成第一存储器访问之后立即启动第二存储器访问。 如果第二时钟信号的上升沿在第二时间段内发生，则第二存储器访问被延迟直到第一时钟信号的第二上升沿。 第一和第二存储器访问的持续时间不依赖于时钟信号的占空比。

公开(公告)号：WO2007070886A2

公开(公告)日：2007-06-21

申请号：PCT/US2006062220

申请日：2006-12-18

申请人： ACTEL CORP ,  LEE POONGYEUB ,  LIU MING-CHI

发明人： LEE POONGYEUB ,  LIU MING-CHI

IPC分类号： H03K19/00

CPC分类号： G11C7/22 ,  G11C7/04 ,  G11C7/08 ,  G11C7/12 ,  G11C8/18 ,  G11C2207/061 ,  G11C2207/2281 ,  H03K2005/00039

摘要： An address transition detector circuit includes an input node, an output node, a bandgap reference node, and P bias and N bias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the P bias node and the N bias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.

摘要翻译： 地址转换检测器电路包括具有从带隙参考节点导出的电压的输入节点，输出节点，带隙参考节点和P SUB偏置和N SUB偏置节点。 第一到第五级联反相器各自由p沟道和n沟道MOS偏置晶体管供电，其栅极分别耦合到P偏置偏压节点和N SUB偏置节点。 第一反相器的输入耦合到输入节点。 第一和第二电容器从第一和第四级联逆变器的输出分别耦合到地。 NAND门具有耦合到输入节点的第一输入，耦合第五级联反相器的输出的第二输入和耦合到输出节点的输出。

公开(公告)号：WO2002069341A2

公开(公告)日：2002-09-06

申请号：PCT/US2002/002764

申请日：2002-02-01

申请人： MICRON TECHNOLOGY, INC.

发明人： JANZEN, Jeffery, W. ,  MANNING, Troy, A. ,  MARTIN, Chris, G. ,  KEETH, Brent

IPC分类号： G11C7/22

CPC分类号： G11C7/1066 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/409 ,  G11C2207/107 ,  G11C2207/2254 ,  G11C2207/2281

摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.

摘要翻译： 通过使用至少一个标志信号来使高速同步存储器子系统中的多个存储器件的读取等待时间被均衡。 标志信号具有等效信号传播特性的读时钟信号，从而自动补偿信号传播的影响。 在检测到标志信号之后，存储器件将以预定数量的时钟周期开始输出与先前接收到的读取命令相关联的数据。 对于每个标志信号，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取延迟之间所需的延迟。 然后将延迟应用于在存储器系统的常规操作期间读取事务。

公开(公告)号：WO01075895A3

公开(公告)日：2002-03-21

申请号：PCT/US2001/010038

申请日：2001-03-30

IPC分类号： G11C16/02 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C8/18 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC分类号： G11C7/106 ,  G06F13/1615 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/4243 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/18 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/105 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2216/22

摘要： A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the synchronous memory device comprises an array of memory cells arranged in rows and columns. A clock connection is provided to receive an externally provided clock signal. The memory does not require a precharge time period during a time period between the first and second externally provided active commands.

摘要翻译： 同步闪速存储器包括非易失性存储器单元阵列。 存储器件具有与SDRAM兼容的封装配置。 在一个实施例中，同步存储器件包括以行和列排列的存储单元阵列。 提供时钟连接以接收外部提供的时钟信号。 存储器在第一和第二外部提供的有效命令之间的时间段期间不需要预充电时间段。

公开(公告)号：WO02005283A1

公开(公告)日：2002-01-17

申请号：PCT/CA2001/000990

申请日：2001-07-06

IPC分类号： G11C11/419 ,  G11C7/22 ,  G11C8/18 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409

CPC分类号： G11C7/1072 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065 ,  G11C2207/2281

摘要： A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.

摘要翻译： 一种用于在半导体存储器中同步行和列存取操作的电路，该半导体存储器具有阵列的位线对，字线，存储单元，读出放大器和用于为读出放大器供电的读出放大器电源电路，该电路包括第一延迟 用于将字线定时脉冲延迟第一预定周期的电路，用于逻辑地组合字线定时脉冲和延迟字线定时脉冲以产生读出放大器使能信号的第一逻辑电路，用于使读出放大器电源电路， 用于将字线定时脉冲延迟第二预定周期的第二延迟电路和用于逻辑组合字线定时脉冲和第二延迟字线定时脉冲以产生列选择使能信号的第二逻辑电路， 多个列访问装置，其中选择第二预定时间段，使得多个列访问装置中的一个 在读出放大器电源电路使能后，ss器件被激活。

公开(公告)号：WO01080249A1

公开(公告)日：2001-10-25

申请号：PCT/JP2000/002577

申请日：2000-04-19

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C29/00 ,  G11C11/409 ,  G11C11/419 ,  G11C16/10

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C2207/2281 ,  G11C2207/229

摘要： When data is written into a memory device, n-bit data is transformed into (n+m)-bit data of a preset pattern, the preset pattern being a pattern containing more logical values having a smaller consumption current value than the other logical values, out of all the data patterns of (n+m) bits. The (n+m)-bit data is, when read out, inversely transformed into the original n-bit data. Accordingly, since logical value write/read which must consume a large current becomes less frequent when writing/reading data to/from a memory device, power consumption can be decreased.

摘要翻译： 当将数据写入存储器件时，将n位数据变换为预设模式的（n + m）位数据，该预置模式是包含比其它逻辑值更小的消耗电流值的更多逻辑值的模式 （n + m）位的所有数据模式中。 当读出时，（n + m）位数据被逆变换成原始n位数据。 因此，由于在从存储器件写入/读取数据时，必须消耗大电流的逻辑值写入/读取变得不那么频繁，所以可以降低功耗。

公开(公告)号：WO99014759A1

公开(公告)日：1999-03-25

申请号：PCT/US1998/019575

申请日：1998-09-18

IPC分类号： G06F1/10 ,  G11C7/22 ,  H03K5/13 ,  H03L7/07 ,  H03L7/081 ,  G11C7/00

CPC分类号： G06F1/10 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229 ,  H03K5/131 ,  H03L7/07 ,  H03L7/0812

摘要： A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments withrespect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing of a digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device. The fine delay circuit includes a multi-tapped delay line coupled to a multiplexer that selects one of the taps for use in generating the delayed clock. When the first or last tap is selected, the timing of the coarse delay circuit is adjusted. The coarse delay circuit includes a counter that generates the digital signal upon counting from an initial count to the terminal count. The coarse delay circuit is adjusted by adjusting the initial count of the counter.

摘要翻译： 可变延迟电路由精细延迟电路和粗略延迟电路构成。 精细延迟电路相对于输入时钟信号以相对小的相位增量来调整延迟时钟信号的延迟。 粗延迟电路以相对大的相位增量来调整数字信号的定时。 延迟时钟信号用于对应用数字信号的寄存器进行时钟，以响应于调整精细延迟电路和粗略延迟电路的定时来控制通过寄存器定时的数字信号的定时。 最初通过改变精细延迟电路的延迟来调整定时关系。 每当达到精细延迟电路的最大或最小延迟时，调整粗略延迟电路。 可变延迟电路可以用于存储器件中以控制将读取数据应用于存储器件的数据总线的定时。 精细延迟电路包括耦合到多路复用器的多抽头延迟线，其选择一个抽头用于产生延迟的时钟。 当选择第一或最后一个抽头时，调整粗延迟电路的定时。 粗延迟电路包括从初始计数到终端计数的计数时产生数字信号的计数器。 通过调整计数器的初始计数来调整粗略延迟电路。