SEMICONDUCTOR STORAGE AND ITS REFRESHING METHOD
    41.
    发明申请
    SEMICONDUCTOR STORAGE AND ITS REFRESHING METHOD 审中-公开
    半导体存储及其修复方法

    公开(公告)号:WO02019340A1

    公开(公告)日:2002-03-07

    申请号:PCT/JP2001/007487

    申请日:2001-08-30

    IPC分类号: G11C11/406

    CPC分类号: G11C11/406

    摘要: A semiconductor storage which can much reduce power consumption on refreshing time more than a conventional semiconductor storage. A cell array (S0) is divided into four blocks (B0-B03),and a cell array (S1) is divided into four blocks (B10-B13). On normal read-out/write-in time, one cell array is selected by address data for specifying a word line, and one block of a selected cell array is selected as well as one word line in the block. On refreshing time, the other cell array is selected, and the four blocks of the selected cell array are refreshed simultaneously. That is, one word line is selected from each of the four blocks, and the selected word line is refreshed. Thus, power consumption is much reduced more than where a plurality of cell arrays are refreshed simultaneously.

    摘要翻译: 半导体存储器比传统的半导体存储器更能在更新时间上大大降低功耗。 单元阵列(S0)被划分为四个块(B0-B03),单元阵列(S1)被分成四个块(B10-B13)。 在正常的读出/写入时间,通过用于指定字线的地址数据选择一个单元阵列,并且选择单元阵列的一个块以及该块中的一个字线。 在更新时间上,选择另一个单元阵列,同时刷新所选单元阵列的四个块。 也就是说,从四个块中的每一个中选择一个字线,并且刷新所选择的字线。 因此,与同时刷新多个单元阵列相比,功耗大大降低。

    TIMER CIRCUIT AND SEMICONDUCTOR MEMORY INCORPORATING THE TIMER CIRCUIT
    42.
    发明申请
    TIMER CIRCUIT AND SEMICONDUCTOR MEMORY INCORPORATING THE TIMER CIRCUIT 审中-公开
    定时器电路和计时器电路的半导体存储器

    公开(公告)号:WO02013384A1

    公开(公告)日:2002-02-14

    申请号:PCT/JP2001/006706

    申请日:2001-08-03

    摘要: A timer circuit exhibiting a timer period which decreases with a rise of temperature and increases with a fall of temperature. A diode (D) has a current characteristic depending on temperature. The forward current flow through an n-type MOS transistor (N1) constituting the primary side of a current mirror. Depending on the current flowing through the n-type MOS transistor (N1), the current flowing through a p-type MOS transistor (P2) and an n-type MOS transistor (N3) constituting the secondary side of the current mirror is determined. The current flowing through the p-type MOS transistor (P2) and the n-type MOS transistor (N3) is supplied as the operating current of a ring oscillator constituted of inverters (I1-I3). Therefore, the period (timer period) of a clock signal CLK outputted from the ring oscillator reflects the temperature characteristics of the diode (D), and the timer period decreases with a rise of temperature.

    摘要翻译: 显示定时器周期的定时器电路,随着温度的升高而降低,随着温度的下降而增加。 二极管(D)具有取决于温度的电流特性。 正向电流流过构成电流镜的初级侧的n型MOS晶体管(N1)。 根据流过n型MOS晶体管(N1)的电流,确定流过构成电流镜的二次侧的p型MOS晶体管(P2)和n型MOS晶体管(N3)的电流。 供给流过p型MOS晶体管(P2)和n型MOS晶体管(N3)的电流作为由反相器(I1-I3)构成的环形振荡器的工作电流。 因此,从环形振荡器输出的时钟信号CLK的周期(定时器周期)反映二极管(D)的温度特性,定时器周期随温度升高而减小。

    INNER VOLTAGE LEVEL CONTROL CIRCUIT, SEMICONDUCTOR STORAGE, AND METHOD FOR CONTROLLING THEM
    43.
    发明申请
    INNER VOLTAGE LEVEL CONTROL CIRCUIT, SEMICONDUCTOR STORAGE, AND METHOD FOR CONTROLLING THEM 审中-公开
    内置电压电平控制电路,半导体存储器及其控制方法

    公开(公告)号:WO02009119A1

    公开(公告)日:2002-01-31

    申请号:PCT/JP2001/006374

    申请日:2001-07-24

    摘要: A voltage level control circuit and control method by which the power consumption is reduced. When the level of a signal A is "L" and the level of a signal PL inputted from outside the voltage level control circuit changes to "H", the level of a latch signal La outputted from a latch (11) changes to "H" and an N FETs (14, 17, 24) are turned on. As a result, a voltage-dividing circuit comprising resistors (12, 13) for voltage division and current Miller differential amplifiers (20, 27) are turned active, and an "H" signal A for controlling a boost voltage Vbt (word line drive voltage) is outputted. When the boost voltage Vbt rises and reaches a reference voltage Vref2, the voltage V2 goes to an "H" level, and consequently the signal A goes to an L level. Since the level of the signal A changes to the "L" level, the latch (11) is made through. Since the signal PL is at an "L" level, the latch signal La outputted from the latch (11) goes to an "L" level, and the N FETs (14, 17, 24) are turned off. Thus in the time zone when it is unnecessary to operate, the N FETs (14, 17, 24) are kept off, thereby saving the power.

    摘要翻译: 一种降低功耗的电压电平控制电路和控制方法。 当信号A的电平为“L”并且从电压电平控制电路外部输入的信号PL的电平变为“H”时,从锁存器(11)输出的锁存信号La的电平变为“H” “并且N个FET(14,17,24)导通。 结果,包括用于分压的电阻器(12,13)和电流米勒差分放大器(20,27)的分压电路被激活,并且“H”信号A用于控制升压电压Vbt(字线驱动 电压)被输出。 当升压电压Vbt上升并达到参考电压Vref2时,电压V2变为“H”电平,因此信号A变为L电平。 由于信号A的电平变为“L”电平,锁存器(11)被制成。 由于信号PL为“L”电平,所以从闩锁(11)输出的锁存信号La变为“L”电平,N + FET(14,17,24)关闭。 因此,在不需要操作的时区中,N个FET(14,17,24)被保持关闭,从而节省电力。

    METHOD AND APPARATUS FOR REFRESHING A SEMICONDUCTOR MEMORY USING IDLE MEMORY CYCLES
    44.
    发明申请
    METHOD AND APPARATUS FOR REFRESHING A SEMICONDUCTOR MEMORY USING IDLE MEMORY CYCLES 审中-公开
    使用空闲记忆循环刷新半导体存储器的方法和装置

    公开(公告)号:WO0043893A3

    公开(公告)日:2000-12-07

    申请号:PCT/US0001487

    申请日:2000-01-20

    发明人: LEUNG WINGYU

    摘要: A memory system is provided that controls a memory that must be refreshed, such as DRAM, in a manner that does to require extensive external control. In one embodiment, the memory system includes a memory controller and a memory block that are coupled by a system bus. The memory block includes an array of memory cells that must be periodically refreshed to maintain valid data. The memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array. The memory controller monitors the number of idle cycles on the system bus during a predetermined refresh period. If the number of monitored idle cycles is less than a predetermined required number of idle cycles, the memory controller forces the required number of idle cycles on the system bus. As a result, the memory controler ensures that there will always be enough idle cycles in which the memory array can be refreshed.

    摘要翻译: 提供一种存储器系统,其以需要广泛的外部控制的方式来控制必须刷新的存储器,例如DRAM。 在一个实施例中,存储器系统包括存储器控制器和通过系统总线耦合的存储器块。 存储器块包括必须定期刷新以保持有效数据的存储器单元阵列。 存储器块还包括刷新控制电路,其在存储器阵列的空闲周期期间刷新存储器单元。 存储器控制器在预定的刷新周期期间监视系统总线上的空闲周期数。 如果所监视的空闲周期的数量小于预定的空闲周期数,则存储器控制器在系统总线上强制所需的空闲周期数。 结果,存储器控制器确保总是存在足够的空闲周期,其中存储器阵列可被刷新。

    METHOD AND APPARATUS FOR REFRESHING A SEMICONDUCTOR MEMORY USING IDLE MEMORY CYCLES
    45.
    发明申请
    METHOD AND APPARATUS FOR REFRESHING A SEMICONDUCTOR MEMORY USING IDLE MEMORY CYCLES 审中-公开
    使用剩余存储器周期来冷却半导体存储器的方法和设备

    公开(公告)号:WO00043893A2

    公开(公告)日:2000-07-27

    申请号:PCT/US2000/001487

    申请日:2000-01-20

    摘要: A memory system is provided that controls a memory that must be refreshed, such as DRAM, in a manner that does to require extensive external control. In one embodiment, the memory system includes a memory controller and a memory block that are coupled by a system bus. The memory block includes an array of memory cells that must be periodically refreshed to maintain valid data. The memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array. The memory controller monitors the number of idle cycles on the system bus during a predetermined refresh period. If the number of monitored idle cycles is less than a predetermined required number of idle cycles, the memory controller forces the required number of idle cycles on the system bus. As a result, the memory controler ensures that there will always be enough idle cycles in which the memory array can be refreshed.

    摘要翻译: 存储器系统控制要刷新的存储器,例如DRAM,而不需要显着的外部控制。 在一个实施例中,存储器系统包括由系统总线耦合的存储器控​​制器和存储器块。 存储块包括必须周期性刷新的存储单元矩阵,以保持数据的有效性。 存储器块还包括存储器刷新电路,其在阵列的其余周期期间刷新存储器单元。 存储器控制器在预定刷新周期期间控制系统总线上的空闲周期的数量。 如果所述数目小于所需的休息周期的预定数量时,他施加在系统总线上的空闲周期的期望数目。 存储器控制器因此确保总是有足够的空闲周期,在此期间可以刷新存储器单元阵列。

    READ/WRITE BUFFERS FOR COMPLETE HIDING OF THE REFRESH OF A SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SAME
    46.
    发明申请
    READ/WRITE BUFFERS FOR COMPLETE HIDING OF THE REFRESH OF A SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SAME 审中-公开
    读/写缓冲器完全隐藏半导体存储器的刷新和操作相同的方法

    公开(公告)号:WO0019445B1

    公开(公告)日:2000-05-25

    申请号:PCT/US9922894

    申请日:1999-10-01

    摘要: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and the memory controller. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A multi-bank refresh scheme is used to cut down the number of collisions between memory refresh operations and memory data access operations. A read buffer is used to buffer read data, thereby allowing memory refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing memory refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. Both the read buffer and the write buffer can be constructed of DRAM cells.

    摘要翻译: 一种用于处理需要周期性刷新操作的DRAM阵列或其他存储器阵列的刷新的方法和设备,使得刷新不需要显式控制信令,也不需要存储器阵列和存储器控制器之间的握手通信。 该方法和设备处理外部访问和刷新操作,使得刷新操作在任何条件下都不干扰外部访问。 结果,SRAM兼容设备可以由DRAM或单晶体管单元构建。 多组刷新方案用于减少内存刷新操作和内存数据访问操作之间的冲突次数。 读缓冲器用于缓冲读数据,从而允许在连续读访问长时间击中特定存储体的地址范围时执行存储器刷新操作。 写入缓冲器用于缓冲写入数据,从而允许在连续写入访问长时间击中特定存储器区块的地址范围时执行存储器刷新操作。 读缓冲器和写缓冲器都可以由DRAM单元构成。

    METHOD AND APPARATUS FOR INCREASING THE TIME AVAILABLE FOR REFRESH FOR 1-T SRAM COMPATIBLE DEVICES
    47.
    发明申请
    METHOD AND APPARATUS FOR INCREASING THE TIME AVAILABLE FOR REFRESH FOR 1-T SRAM COMPATIBLE DEVICES 审中-公开
    用于增加1-T SRAM兼容设备刷新时间的方法和装置

    公开(公告)号:WO00025317A1

    公开(公告)日:2000-05-04

    申请号:PCT/US1999/024310

    申请日:1999-10-18

    CPC分类号: G11C11/406 G11C7/1039

    摘要: In a burst read transaction, all the data in the burst transaction is prefetched from a DRAM memory into the read buffer in one memory cycle. The DRAM array can therefore be refreshed while the burst read data is sequentially transferred from the read buffer to the I/Q interface. In a burst write transaction, multiple burst write data values are written to a write buffer over multiple I/O cycles. This burst write data is not simultaneously retired to the DRAM array until the next write transaction. As a result, the DRAM array is only engaged in the burst write transaction for one memory cycle. The DRAM array can therefore be refreshed during one or more of the remaining three I/O cycles.

    摘要翻译: 在突发读取事务中,突发事件中的所有数据在一个存储器周期中从DRAM存储器预取到读缓冲器。 因此,可以在突发读取数据从读取缓冲器顺序地传送到I / Q接口的同时刷新DRAM阵列。 在突发写入事务中,多个突发写入数据值通过多个I / O周期写入写入缓冲区。 这个突发写入数据不会同时退出到DRAM阵列直到下一次写入事务。 结果,DRAM阵列仅在一个存储器周期中进行突发写入事务。 因此,可以在剩余的三个I / O周期中的一个或多个期间刷新DRAM阵列。

    A DYNAMIC RANDOM ACCESS MEMORY SYSTEM WITH SIMULTANEOUS ACCESS AND REFRESH OPERATIONS AND METHODS FOR USING THE SAME
    48.
    发明申请
    A DYNAMIC RANDOM ACCESS MEMORY SYSTEM WITH SIMULTANEOUS ACCESS AND REFRESH OPERATIONS AND METHODS FOR USING THE SAME 审中-公开
    具有同时访问和刷新操作的动态随机访问存储器系统及其使用方法

    公开(公告)号:WO99060573A1

    公开(公告)日:1999-11-25

    申请号:PCT/US1999/010892

    申请日:1999-05-17

    CPC分类号: G11C11/406

    摘要: A memory (200) including an array (201) of rows and columns of 2-transistor, 1-capacitor memory cells (301) of the cells of each row coupled to first and second wordlines (303a, 303b) and the cells of each column coupled to a pair of bitlines (302a, 302b). Refresh circuitry (208) activates the first wordline (303a) plus selected said row and refreshes the cells (301) of that row through a first one of the bitlines (302a) of each of the columns. Data access circuitry (202, 204) substantially simultaneously activates the second said wordline (303b) of a second selected row and accesses selected cells of the second row through a second one of the bitlines (302b) in the corresponding columns.

    摘要翻译: 一种存储器(200),包括耦合到第一和第二字线(303a,303b)的每行的单元的单元的每个行的单元的行和列的行和列的阵列(201)和每个单元的每个单元的单元 列耦合到一对位线(302a,302b)。 刷新电路(208)激活第一字线(303a)加上所选择的行,并且通过每列的位线(302a)中的第一位刷新行的单元(301)。 数据访问电路(202,204)基本上同时激活第二选定行的第二所述字线(303b),并通过相应列中的位线(302b)中的第二行访问第二行的选定单元。

    A LOW LATENCY DRAM CELL AND METHOD THEREFOR
    49.
    发明申请
    A LOW LATENCY DRAM CELL AND METHOD THEREFOR 审中-公开
    低延迟DRAM单元及其方法

    公开(公告)号:WO99009560A1

    公开(公告)日:1999-02-25

    申请号:PCT/US1998/015979

    申请日:1998-07-31

    摘要: A memory cell and structure are implemented to provide a memory system having the advantages of both static and dynamic memories. A dynamic memory cell is implemented using a capacitor to store charge associated with a data value stored in the cell. The storage capacitor is accessible through multiple switches, and each of the switches is coupled to an independent bitline. Because independent bitlines are implemented, one bitline may sense the data value stored within the memory cell, while a second bitline is pre-charged, or refreshed, for a next memory operation to be performed. Thus, as soon as data is provided to the first bitline, any memory cells sharing the second bitline are ready to be sensed and restored even though they are all in the same data memory array. Such sequential operation is not possible with prior art DRAM memory cells because they require a refresh period in which to pre-charge bitlines accessing the same memory location. By providing the ability to access the same memory cell during a next subsequent timing cycle, a DRAM cell having a very low latency is implemented.

    摘要翻译: 实现存储单元和结构以提供具有静态和动态存储器的优点的存储器系统。 使用电容器来实现动态存储器单元以存储与存储在单元中的数据值相关联的电荷。 存储电容器可通过多个开关访问,并且每个开关耦合到独立的位线。 由于实现了独立的位线,所以一个位线可以感测存储在存储器单元中的数据值,而第二位线被预先充电或刷新以用于要执行的下一个存储器操作。 因此,只要数据被提供给第一位线,即使共享第二位线的任何存储单元都处于相同的数据存储器阵列中,也可以被感测和恢复。 这种顺序操作对于现有技术的DRAM存储器单元是不可能的,因为它们需要刷新周期来预充电访问相同存储器位置的位线。 通过提供在下一个后续定时周期期间访问相同存储单元的能力,实现了具有非常低延迟的DRAM单元。

    MEMORY
    50.
    发明申请
    MEMORY 审中-公开
    记忆

    公开(公告)号:WO1998019309A1

    公开(公告)日:1998-05-07

    申请号:PCT/JP1997003954

    申请日:1997-10-30

    IPC分类号: G11C11/407

    CPC分类号: G11C7/1075 G11C11/406

    摘要: A memory wherein the refresh control is improved by integrating a multiport DRAM and a general-purpose DRAM into one chip and making the X addresses of the two kinds of DRAMs consecutive and making the Y addresses common and making the control terminals common, excellence in cost performance being attained by mounting a DRAM used as a temporary buffer mixedly thereby reducing the board area, without marring the strong point of a conventional multiport DRAM.

    摘要翻译: 通过将多端口DRAM和通用DRAM集成到一个芯片中并使两种DRAM的X地址连续并使得Y地址共同并使控制端子共同,成本优越的存储器 通过将用作临时缓冲器的DRAM混合从而减少电路板面积来实现性能,而不损害常规多端口DRAM的强点。