摘要:
A semiconductor storage which can much reduce power consumption on refreshing time more than a conventional semiconductor storage. A cell array (S0) is divided into four blocks (B0-B03),and a cell array (S1) is divided into four blocks (B10-B13). On normal read-out/write-in time, one cell array is selected by address data for specifying a word line, and one block of a selected cell array is selected as well as one word line in the block. On refreshing time, the other cell array is selected, and the four blocks of the selected cell array are refreshed simultaneously. That is, one word line is selected from each of the four blocks, and the selected word line is refreshed. Thus, power consumption is much reduced more than where a plurality of cell arrays are refreshed simultaneously.
摘要:
A timer circuit exhibiting a timer period which decreases with a rise of temperature and increases with a fall of temperature. A diode (D) has a current characteristic depending on temperature. The forward current flow through an n-type MOS transistor (N1) constituting the primary side of a current mirror. Depending on the current flowing through the n-type MOS transistor (N1), the current flowing through a p-type MOS transistor (P2) and an n-type MOS transistor (N3) constituting the secondary side of the current mirror is determined. The current flowing through the p-type MOS transistor (P2) and the n-type MOS transistor (N3) is supplied as the operating current of a ring oscillator constituted of inverters (I1-I3). Therefore, the period (timer period) of a clock signal CLK outputted from the ring oscillator reflects the temperature characteristics of the diode (D), and the timer period decreases with a rise of temperature.
摘要:
A voltage level control circuit and control method by which the power consumption is reduced. When the level of a signal A is "L" and the level of a signal PL inputted from outside the voltage level control circuit changes to "H", the level of a latch signal La outputted from a latch (11) changes to "H" and an N FETs (14, 17, 24) are turned on. As a result, a voltage-dividing circuit comprising resistors (12, 13) for voltage division and current Miller differential amplifiers (20, 27) are turned active, and an "H" signal A for controlling a boost voltage Vbt (word line drive voltage) is outputted. When the boost voltage Vbt rises and reaches a reference voltage Vref2, the voltage V2 goes to an "H" level, and consequently the signal A goes to an L level. Since the level of the signal A changes to the "L" level, the latch (11) is made through. Since the signal PL is at an "L" level, the latch signal La outputted from the latch (11) goes to an "L" level, and the N FETs (14, 17, 24) are turned off. Thus in the time zone when it is unnecessary to operate, the N FETs (14, 17, 24) are kept off, thereby saving the power.
摘要:
A memory system is provided that controls a memory that must be refreshed, such as DRAM, in a manner that does to require extensive external control. In one embodiment, the memory system includes a memory controller and a memory block that are coupled by a system bus. The memory block includes an array of memory cells that must be periodically refreshed to maintain valid data. The memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array. The memory controller monitors the number of idle cycles on the system bus during a predetermined refresh period. If the number of monitored idle cycles is less than a predetermined required number of idle cycles, the memory controller forces the required number of idle cycles on the system bus. As a result, the memory controler ensures that there will always be enough idle cycles in which the memory array can be refreshed.
摘要:
A memory system is provided that controls a memory that must be refreshed, such as DRAM, in a manner that does to require extensive external control. In one embodiment, the memory system includes a memory controller and a memory block that are coupled by a system bus. The memory block includes an array of memory cells that must be periodically refreshed to maintain valid data. The memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array. The memory controller monitors the number of idle cycles on the system bus during a predetermined refresh period. If the number of monitored idle cycles is less than a predetermined required number of idle cycles, the memory controller forces the required number of idle cycles on the system bus. As a result, the memory controler ensures that there will always be enough idle cycles in which the memory array can be refreshed.
摘要:
A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and the memory controller. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A multi-bank refresh scheme is used to cut down the number of collisions between memory refresh operations and memory data access operations. A read buffer is used to buffer read data, thereby allowing memory refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing memory refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. Both the read buffer and the write buffer can be constructed of DRAM cells.
摘要:
In a burst read transaction, all the data in the burst transaction is prefetched from a DRAM memory into the read buffer in one memory cycle. The DRAM array can therefore be refreshed while the burst read data is sequentially transferred from the read buffer to the I/Q interface. In a burst write transaction, multiple burst write data values are written to a write buffer over multiple I/O cycles. This burst write data is not simultaneously retired to the DRAM array until the next write transaction. As a result, the DRAM array is only engaged in the burst write transaction for one memory cycle. The DRAM array can therefore be refreshed during one or more of the remaining three I/O cycles.
摘要:
A memory (200) including an array (201) of rows and columns of 2-transistor, 1-capacitor memory cells (301) of the cells of each row coupled to first and second wordlines (303a, 303b) and the cells of each column coupled to a pair of bitlines (302a, 302b). Refresh circuitry (208) activates the first wordline (303a) plus selected said row and refreshes the cells (301) of that row through a first one of the bitlines (302a) of each of the columns. Data access circuitry (202, 204) substantially simultaneously activates the second said wordline (303b) of a second selected row and accesses selected cells of the second row through a second one of the bitlines (302b) in the corresponding columns.
摘要:
A memory cell and structure are implemented to provide a memory system having the advantages of both static and dynamic memories. A dynamic memory cell is implemented using a capacitor to store charge associated with a data value stored in the cell. The storage capacitor is accessible through multiple switches, and each of the switches is coupled to an independent bitline. Because independent bitlines are implemented, one bitline may sense the data value stored within the memory cell, while a second bitline is pre-charged, or refreshed, for a next memory operation to be performed. Thus, as soon as data is provided to the first bitline, any memory cells sharing the second bitline are ready to be sensed and restored even though they are all in the same data memory array. Such sequential operation is not possible with prior art DRAM memory cells because they require a refresh period in which to pre-charge bitlines accessing the same memory location. By providing the ability to access the same memory cell during a next subsequent timing cycle, a DRAM cell having a very low latency is implemented.
摘要:
A memory wherein the refresh control is improved by integrating a multiport DRAM and a general-purpose DRAM into one chip and making the X addresses of the two kinds of DRAMs consecutive and making the Y addresses common and making the control terminals common, excellence in cost performance being attained by mounting a DRAM used as a temporary buffer mixedly thereby reducing the board area, without marring the strong point of a conventional multiport DRAM.