公开(公告)号：WO0146706A3

公开(公告)日：2002-08-01

申请号：PCT/US0042830

申请日：2000-12-22

Applicant: MENTOR GRAPHICS CORP

Inventor： SCHELLENBERG FRANKLIN MARK ,  MOORE ANDREW J

IPC: G03F1/08 ,  G01R31/311 ,  G01N21/956 ,  G03F1/00

CPC classification number: G01R31/311

Abstract: Design-based reticle inspection allows for a more efficient prioritization than typical human labor intensive reticle inspection techniques. A processed netlist for an integrated circuit (IC) and/or layout of the IC is used to determine the relative priorities of reticle defects identified by a reticle inspection device. In one embodiment, the processed netlist is a netlist that is derived by a verification tool based on a layout of the IC design. The processed netlist can include component coordinates that indicate the position of the components of the IC. In one embodiment, the processed layout includes derived geometry, for example, critical dimensions and/or device identifications that can be used to determine regions of interest. In one embodiment, defects are prioritized based on the location of the defects with respect to functional portions of the integrated circuit. For example, regions of interest can be determined around certain IC structures (e.g., transistor gates, minimum dimension lines, line corners). In one embodiment, defects within the regions of interest can be repaires while defects outside of the care zone can be ignored. More complex defect prioritization can be provided by prioritizing defects, for example, by size within the regions of interest. By prioritizing defects by areas of interest, the number of defects analyzed by a human operator and/or simulator can be decreased thereby decreasing the cost of reticle inspection and repair.

Abstract translation: 基于设计的掩模版检查允许比典型的人力密集型掩模版检查技术更有效的优先级。 用于IC的集成电路（IC）和/或布局的处理网表用于确定由掩模版检查装置识别的掩模版缺陷的相对优先级。 在一个实施例中，经处理的网表是基于IC设计的布局由验证工具导出的网表。 经处理的网表可以包括指示IC的组件的位置的组件坐标。 在一个实施例中，经处理的布局包括导出的几何形状，例如可用于确定感兴趣区域的关键尺寸和/或设备标识。 在一个实施例中，基于缺陷相对于集成电路的功能部分的位置优先考虑缺陷。 例如，可以围绕某些IC结构（例如，晶体管栅极，最小尺寸线，线角）来确定感兴趣的区域。 在一个实施例中，感兴趣区域内的缺陷可以是修复，而护理区外的缺陷可以被忽略。 可以通过对缺陷进行优先排序来提供更复杂的缺陷优先级，例如按照感兴趣区域内的大小。 通过将感兴趣区域的缺陷设定为优先级，可以减少由操作人员和/或模拟器分析的缺陷的数量，从而降低掩模版检查和修复的成本。

公开(公告)号：WO0194955A3

公开(公告)日：2002-04-18

申请号：PCT/US0140909

申请日：2001-06-08

Applicant: UNIV MICHIGAN ,  WHITAKER JOHN N FA ,  YANG KYOUNG ,  KATEHI LINDA P B

Inventor： WHITAKER JOHN FIRMAN ,  YANG KYOUNG ,  KATEHI LINDA P B

IPC: G01R1/07 ,  G01R13/34 ,  G01R29/08 ,  G01R29/14 ,  G01R31/311

CPC classification number: G01R29/14 ,  G01R1/071 ,  G01R13/347 ,  G01R29/0885 ,  G01R31/311

Abstract: A microwave and millimeter-wave electric-field mapping system based on electro-optic sampling has been developed using micromachined Gallium Arsenide crystals mounted on gradient index lenses and single-mode optical fibers. The probes are able to detect three orthogonal polarizations of electric fields and, due to the flexibility and size of the optical fiber, can be positioned not only from the extreme near-field to the far-field regions of microwave and millimeter-wave structures, but also inside of enclosures such as waveguides and packages. A microwave electric-field-mapping system based on micromachined GaAs electro-optic sampling probes mounted on gradient index lenses and single-mode optical fibers can extract field images from the interior of an enclosed microwave cavity.

Abstract translation: 已经使用安装在梯度折射率透镜和单模光纤上的微加工砷化镓晶体开发了基于电光采样的微波和毫米波电场映射系统。 探头能够检测电场的三个正交极化，并且由于光纤的灵活性和尺寸，不仅可以定位在微波和毫米波结构的远场区域的极端近场， 而且还在诸如波导和封装的外壳内部。 基于安装在梯度折射率透镜和单模光纤上的微加工GaAs电光采样探针的微波电场映射系统可以从封闭的微波腔内部提取场图像。

公开(公告)号：WO0148465A3

公开(公告)日：2002-02-21

申请号：PCT/IL0000855

申请日：2000-12-22

Applicant: ORBOTECH LTD ,  GUTMAN ZEEV ,  GILAT BERNSHTEIN TALLY

Inventor： GUTMAN ZEEV ,  GILAT-BERNSHTEIN TALLY

IPC: G01N21/956 ,  G01R31/311 ,  G06T7/00 ,  G01N21/95

CPC classification number: G06T7/0006 ,  G01N21/95607 ,  G01N21/95684 ,  G01N2021/95615 ,  G01N2021/95638 ,  G01R31/311 ,  G06T2207/30148

Abstract: This invention discloses an electrical circuit inspection system including an optical subsystem for optically inspecting an electrical circuit and providing an inspection output identifying more than two different types of regions and an analysis subsystem for analyzing the inspection output, the analyzing including comparing the inspection output with a computer file reference identifying more than two different types of regions. A method for inspecting an electrical circuit inspection is also disclosed.

Abstract translation: 本发明公开了一种电路检查系统，包括光学子系统，用于光学检查电路并提供识别两个以上不同类型的区域的检查输出和用于分析检查输出的分析子系统，该分析包括将检查输出与 计算机文件参考标识两个以上不同类型的区域。 还公开了一种检查电路检查的方法。

公开(公告)号：WO01081936A1

公开(公告)日：2001-11-01

申请号：PCT/JP2001/003395

申请日：2001-04-20

IPC: G01R31/308 ,  G01R31/311 ,  G01R31/28

CPC classification number: G01R31/311 ,  G01R31/308

Abstract: A method and apparatus for testing a circuit by detecting radiation from the circuit. A circuit tester (10) comprises a signal source (20), a photodetector (30), and a decision circuit (40). The signal source (20) supplies the circuit (12) with an input signal having a test pattern. The photodetector (30) detects radiation attributed to hot electrons produced by the input signal supplied to the circuit (12), and converts it into an electric signal. The decision circuit (40) determines whether the circuit (12) has any defect based on the pulse width of the converted electric signal. Specifically, a pulse-width measurement circuit (50) determines whether the pulse width of the electric signal exceeded a predetermined width, and a detector (60) detects a defect of the circuit (12) based on the output from the pulse width measurement circuit (50). The detector (60) judges that a circuit (12) is defective if the pulse width of the electric signal of abnormal current in the circuit (12) is long.

Abstract translation: 一种通过检测来自电路的辐射来测试电路的方法和装置。 电路测试器（10）包括信号源（20），光电检测器（30）和判定电路（40）。 信号源（20）向电路（12）提供具有测试图案的输入信号。 光检测器（30）检测由提供给电路（12）的输入信号产生的热电子的辐射，并将其转换为电信号。 判定电路（40）基于转换后的电信号的脉冲宽度来判定电路（12）是否有任何缺陷。 具体地说，脉宽测量电路（50）判定电信号的脉冲宽度是否超​​过预定的宽度，检测器（60）根据脉冲宽度测量电路的输出来检测电路（12）的缺陷 （50）。 如果电路（12）中异常电流的电信号的脉冲宽度较长，则检测器（60）判断电路（12）有缺陷。

公开(公告)号：WO01048465A2

公开(公告)日：2001-07-05

申请号：PCT/IL2000/000855

申请日：2000-12-22

IPC: G01N21/956 ,  G01R31/311 ,  G06T7/00 ,  G01N21/95

CPC classification number: G06T7/0006 ,  G01N21/95607 ,  G01N21/95684 ,  G01N2021/95615 ,  G01N2021/95638 ,  G01R31/311 ,  G06T2207/30148

Abstract: This invention discloses an electrical circuit inspection system including an optical subsystem for optically inspecting an electrical circuit and providing an inspection output identifying more than two different types of regions and an analysis subsystem for analyzing the inspection output, the analyzing including comparing the inspection output with a computer file reference identifying more than two different types of regions. A method for inspecting an electrical circuit inspection is also disclosed.

Abstract translation: 本发明公开了一种电路检查系统，包括光学子系统，用于光学检查电路并提供识别两个以上不同类型的区域的检查输出和用于分析检查输出的分析子系统，该分析包括将检查输出与 计算机文件参考标识两个以上不同类型的区域。 还公开了一种检查电路检查的方法。

公开(公告)号：WO01006271A1

公开(公告)日：2001-01-25

申请号：PCT/US2000/019169

申请日：2000-07-13

IPC: G01R1/04 ,  G01R31/311 ,  G01R31/02

CPC classification number: G01R31/311 ,  G01R1/0433

Abstract: A test socket (11) for testing an optical IC device in a dead bug orientation includes a socket body (13) with a device under test cavity (DUT cavity) (17) for receiving an optical IC device under test (optical DUT) (47) in a contact-up or dead bug orientation. The DUT cavity (17) has a bottom wall (91) with at least one aperture (95) through which the photoactive side of the optical DUT held in the cavity can be illuminated. An outer array of axial contact elements (53) arranged about the DUT cavity provides conductive paths through the socket body. The test socket (11) further includes a plunger assembly (25) insertable into the DUT cavity (17) of the socket body (13) having an inner array of axial contact elements (51) which extend through the plunger assembly and which are configured to provide contact with the contacts on the contact side (45) of the optical DUT. A transverse conductor bridge (55) at the top of the plunger assembly (25) provides a transverse electrical path connecting the inner array of axial contact elements (51) of the plunger assembly and the outer array of axial contact elements (53) of the socket body when the plunger assembly is inserted into the DUT cavity. An electrical path is thereby provided between the contacts of the contact optical DUT and the bottom of the socket body mounted to the DUT board through the plunger assembly and socket body.

Abstract translation: 用于以死虫方向测试光IC器件的测试插座（11）包括具有被测器件（DUT空腔）（17））的插座主体（13），用于接收被测光学IC器件（光DUT）（ 47）在接触或死虫方向。 DUT空腔（17）具有带有至少一个孔（95）的底壁（91），通过所述孔（95）可以照亮保持在空腔中的光学DUT的光敏面。 布置在DUT腔周围的轴向接触元件（53）的外部阵列提供穿过插座主体的导电路径。 测试插座（11）还包括可插入插座主体（13）的DUT空腔（17）中的柱塞组件（25），其具有延伸穿过柱塞组件的轴向接触元件（51）的内部阵列， 以提供与光学DUT的接触侧（45）上的触点的接触。 在柱塞组件（25）的顶部处的横向导体桥（55）提供连接柱塞组件的轴向接触元件（51）的内部阵列和外部阵列的轴向接触元件（53）的横向电气路径 当柱塞组件插入DUT空腔时，插座主体。 因此，通过柱塞组件和插座主体，在接触光学DUT的触点和安装到DUT板的插座主体的底部之间提供电路径。

公开(公告)号：WO01004610A2

公开(公告)日：2001-01-18

申请号：PCT/HU2000/000077

申请日：2000-07-12

IPC: G01N22/00 ,  G01R31/26 ,  G01R31/311

CPC classification number: G01R31/311 ,  G01N22/00 ,  G01R31/2648

Abstract: The invention relates to a method and an arrangement for measuring the recombination lifetime of minority carriers in semiconductors. According to the method the semiconductor is illuminated by pulses of a light source, and the time dependence of the change in the microwave reflection caused by minority carriers generated in the semiconductor by light is detected so that the microwave guide is directly contacted with the semiconductor. Thus microwave reflection occurs from a significantly smaller part of the volume as compared to contact-free methods. The arrangement comprises a microwave generator (2) tunable by a varactor (1), the output of the generator (2) is connected to the input of an isolator (3), the output of which is connected to the first gate of a circulator (4), the second gate of which is connected to a contact needle (5) also through a coaxial cable, whereas the third gate of the circulator (4) is led to a detector (8) through a coaxial connection. The contact needle (5) carries the microwave field in direct contact to the semiconductor (6), which is the impedance closing the microwave path. The semiconductor (6) is optical excited from a laser light source (7), which is connected to one of the outputs of a pulse generator (12), the input of which is connected to the output of a central signal processing unit (13). To the same output, the inputs of the varactor (1) and the laser light source (7) are connected. The detector (8) is connected to the input of a sample and hold circuit (10) via an amplifier (9), which separates the low-frequency noise. The output of the sample and hold circuit (10) is fed back to the input of the amplifier (9). The output of the amplifier (9) is connected to a known transient recorder (11). The control and timing input of transient recorder (11) is connected to the output of pulse generator (12). To this output is connected the timing input of sample and hold circuit (10), as well. Signal processing is performed by the central signal processing unit (13), which also controls varactor (1), laser light source (7) and pulse generator (12).

Abstract translation: 测量半导体中少数载流子复合寿命的方法和装置 根据该方法，通过来自光源的脉冲来照射半导体，并且半导体中由少数载流子引起的微波反射的变化的暂时连接由 光被检测到，使得微波波导直接与半导体接触。 因此，与非接触过程相比，微波反射从体积的很小部分发生。 该装置包括由变容二极管（1）调节的微波发生器（2），发生器（2）的输出端连接到隔离器（3）的输入端，其输出端连接到 循环器（4）的第一栅极，后者的第二栅极也通过同轴电缆连接到接触片（5），而循环器（4）的第三栅极指向检测器 8）通过同轴连接。 接触片（5）使微波场直接与半导体（6）接触，半导体（6）是关闭微波路径的阻抗。 半导体（6）由连接到脉冲发生器（12）的一个输出端的激光源（7）光学激励，脉冲发生器（12）的输入端连接到 中央信号处理单元（13）的输出。 变容二极管（1）和激光光源（7）的输入端也连接到上述CPU的输出端。 检测器（8）经由放大器（9）连接到采样和存储电路（10）的输入端，该放大器分离低频噪声。 采样和存储电路（10）的输出端连接到放大器（9）的输入端。 放大器（9）的输出连接到已知的瞬态记录器（11）。 已知瞬态记录器（11）的控制和同步输入端连接到脉冲发生器（12）的输出端。 在这个输出端，采样和存储电路（10）的同步输入端也被连接。 信号处理由也控制变容二极管（1），激光光源（7）和脉冲发生器（12）的中央信号处理单元（13）执行。

公开(公告)号：WO00072030A1

公开(公告)日：2000-11-30

申请号：PCT/US1999/011299

申请日：1999-05-21

IPC: G01R31/302 ,  G01R31/28 ,  G01R31/311 ,  H01L21/822 ,  H01L27/04 ,  G01R31/316

CPC classification number: G01R31/3025 ,  G01R31/2884 ,  G01R31/311 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system for testing a microelectronic circuit includes a test bed for mounting a microelectronic circuit, and a signal source for applying a signal to a microelectronic circuit mounted on the test bed. The system additionally includes a test probe for wirelessly receiving electromagnetic response signals from the microelectronic circuit mounted on the test bed. In a preferred form, the electromagnetic response signals are radio-frequency signals. The test system additionally includes a computer connected to the test probe for analyzing the electromagnetic response signals. An integrated circuit for testing on the test system has a test circuit portion that emits electromagnetic radiation in response to a predetermined signal applied to the test circuit.

Abstract translation: 用于测试微电子电路的系统包括用于安装微电子电路的测试台和用于将信号施加到安装在测试台上的微电子电路的信号源。 该系统还包括用于从安装在测试台上的微电子电路无线地接收电磁响应信号的测试探针。 在优选形式中，电磁响应信号是射频信号。 测试系统还包括连接到测试探针的计算机，用于分析电磁响应信号。 用于在测试系统上测试的集成电路具有响应于施加到测试电路的预定信号而发射电磁辐射的测试电路部分。

公开(公告)号：WO00046608A1

公开(公告)日：2000-08-10

申请号：PCT/IB1999/001830

申请日：1999-11-15

IPC: G01R31/311 ,  H05K1/00 ,  H05K1/02

CPC classification number: G01R31/311 ,  H05K1/0269 ,  H05K1/0298

Abstract: A novel optical inspection technique for multi-layer wafers and the like in which conductor patterns of a top layer only are to be inspected, such layer being upon an intermediate transparent or translucent insulation layer in turn upon a base layer(s) thereunder, wherein the intermediate layer only is fluoresced, displaying the top layer conductors as dark in the field of fluorescent light, and causing reflections from layers below the intermediate layer effectively to disappear to obviate confusion with the top layer conductors to be inspected.

Abstract translation: 一种用于多层晶片等的新颖的光学检查技术，其中只需要检查顶层的导体图案，这样的层依次在中间透明或半透明绝缘层上，其基底层在其上，其中 中间层仅发荧光，在荧光领域显示顶层导体为暗，并且有效地引起来自中间层下面的层的反射消失以消除与待检查的顶层导体的混淆。

公开(公告)号：WO00020879A1

公开(公告)日：2000-04-13

申请号：PCT/US1999/012372

申请日：1999-07-08

IPC: G01R33/035 ,  G01N13/22 ,  G01N27/82 ,  G01R19/08 ,  G01R31/307 ,  G01R33/10 ,  G06T5/00 ,  G06T5/20 ,  H01L21/66 ,  G01N27/72

CPC classification number: G01R31/311 ,  G01N27/82 ,  G01R19/08 ,  G01R31/307 ,  G01R33/10

Abstract: A method of, and an apparatus for, creating an image of currents flowing through current paths in a microelectronic circuit such that the image of the currents has improved spatial resolution using filter. The filters (40) increase the spatial resolution and eliminate noise and edge artifacts in magnetic field and electric field images of electronic circuits. In accordance with the method, a magnetic field image is created with a scanning SQUID microscope (32). A magnetic inversion technique is then used to convert the magnetic field image into a current density image. The current density image is filtered based upon known restrictions on the wiring geometry of the microelectronic circuit being imaged. The technique can also be applied to convert electric fields of a circuit from a scanning single electron transistor microscope into images of the voltage levels on the wires in the circuit.

Abstract translation: 一种用于产生流过微电子电路中的电流路径的电流的图像的方法和装置，使得电流的图像使用滤波器具有改善的空间分辨率。 滤波器（40）增加空间分辨率并消除电子电路的磁场和电场图像中的噪声和边缘伪像。 根据该方法，用扫描SQUID显微镜（32）产生磁场图像。 然后使用磁反转技术将磁场图像转换成电流密度图像。 基于对正在成像的微电子电路的布线几何形状的已知限制，对电流密度图像进行滤波。 该技术也可以用于将扫描单电子晶体管显微镜的电路的电场转换成电路中的电线上的电压电平的图像。