公开(公告)号：WO2023044219A1

公开(公告)日：2023-03-23

申请号：PCT/US2022/075079

申请日：2022-08-17

Applicant: QUALCOMM INCORPORATED

Inventor： ZHANG, Qian ,  ZHOU, Yan ,  LI, Junyi ,  DAMNJANOVIC, Jelena ,  AKKARAKARAN, Sony ,  ABEDINI, Navid ,  LUO, Tao

IPC: H04W76/14

Abstract: Methods, systems, and devices for wireless communication at a user equipment (UE) are described. A first user equipment (UE) may transmit, to a set of UEs, an indication of a first semi-static traffic pattern between the first UE and a second UE. In some examples, the first semi-static traffic pattern may indicate a pattern for transmission or reception between the first UE and the second UE using a beam pair during a time period. The first UE may receive a response, from one or more UEs, indicating one or more semi-static traffic patterns for the time period. The first UE may then transmit, to a third UE of the one or more UEs, an indication of selection of a second semi-static traffic pattern for communication between the first UE and the third UE during the time period.

公开(公告)号：WO2023019161A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/074748

申请日：2022-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LEE, Hyunyoo ,  KIM, Kang-Yong ,  LU, Yang

IPC: G06F3/06

Abstract: Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

公开(公告)号：WO2022120325A1

公开(公告)日：2022-06-09

申请号：PCT/US2021/072596

申请日：2021-11-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GYLLENSKOG, Christian, M.

IPC: G06F3/06 ,  G06F7/78

Abstract: Methods, systems, and devices for queue configuration for host interface are described. An apparatus may include a host system including a first circular queue having a first entry that indicates a first command for a memory system and a location of data associated with the first command. The apparatus may include a controller that may access the first entry of the first circular queue and generate a second command for the memory system based on the data associated with the first command and the first entry. The controller may then transmit the second command to the memory system based on generating the command. The controller may also receive a response from the memory system based on transmitting the command. The controller may remove the first entry from the first circular queue based on receiving the response from the memory system.

公开(公告)号：WO2022039993A1

公开(公告)日：2022-02-24

申请号：PCT/US2021/045517

申请日：2021-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BOEHM, Aaron, P. ,  BUCH, Steffen ,  DOVER, Lance, W.

IPC: G06F21/44 ,  G06F21/60 ,  G06F12/14

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

公开(公告)号：WO2021252163A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/033457

申请日：2021-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YAMAMOTO, Nobuo ,  MORGAN, Donald, Martin ,  WONG, Victor ,  KWAK, Jongtae

IPC: G11C11/22 ,  G06F11/10 ,  G11C11/221 ,  G11C11/401 ,  G11C16/10 ,  G11C16/26 ,  G11C29/20 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

公开(公告)号：WO2023003710A2

公开(公告)日：2023-01-26

申请号：PCT/US2022/036561

申请日：2022-07-08

Applicant: QUALCOMM INCORPORATED

Inventor： SRIDHARAN, Gokul ,  LY, Hung Dinh ,  GAAL, Peter ,  CHEN, Wanshi

Abstract: Methods, systems, and devices for wireless communications are described. Generally, a user equipment (UE) may be configured to transmit two or more consecutive transmissions that may be used for demodulation reference signal (DMRS) bundling. If criteria for DMRS bundling are not satisfied, the UE may generate dummy data to transmit during the skipped configured grant occasion, and may maintain phase continuity across the skipped configured grant occasion and any other PUSCHs in a set of uplink transmissions. In some examples, the UE may deprioritize DMRS bundling for sets of PUSCHs during which a PUSCH is to be skipped. If criteria for DMRS bundling are not satisfied, the UE may not maintain phase continuity across the set of PUSCHs, and may refrain from transmitting any data during the CG-PUSCH occasion.

公开(公告)号：WO2022265798A1

公开(公告)日：2022-12-22

申请号：PCT/US2022/029860

申请日：2022-05-18

Applicant: QUALCOMM INCORPORATED

Inventor： LUO, Jianghong ,  ABEDINI, Navid ,  LI, Junyi ,  LUO, Tao

IPC: H04B7/155

Abstract: Methods, systems, and devices for wireless communications are described. A repeater may extend coverage of wireless communications services between two wireless nodes (e.g., a base station and a user equipment (UE)). A network control node (e.g., a base station) may receive a first indication of a capability of a repeater to detect a time division duplexing (TDD) pattern of a channel between the base station and the UE. The base station may transmit, to the UE and via the repeater, one or more parameters associated with the UE performing one or more channel measurements and reference signals for the channel measurements. The base station may transmit, to the repeater, a second indication of a TDD pattern of the channel based on the capability of the repeater. Based on the indication of the TDD pattern, the repeater may adjust one or more radio frequency components of the repeater.

公开(公告)号：WO2022251791A1

公开(公告)日：2022-12-01

申请号：PCT/US2022/072384

申请日：2022-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FRATIN, Lorenzo ,  FANTINI, Paolo ,  VARESI, Enrico

IPC: H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices for techniques that support sidewall structures for memory cells in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. The self-selecting storage element may extend between the first electrode and the second electrode in a direction that is parallel with a plane defined by the substrate. The self-selecting storage element may also include a bulk region and a sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. Also, the sidewall region may extend between the first electrode and the second electrode.

公开(公告)号：WO2022165479A1

公开(公告)日：2022-08-04

申请号：PCT/US2022/070322

申请日：2022-01-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SCHAEFER, Scott, E. ,  BOEHM, Aaron, P.

IPC: G06F11/10 ,  G06F9/30 ,  G06F3/06

Abstract: Methods, systems, and devices for metadata storage at a memory device are described to support storage of metadata information and error control information at a memory device. The metadata information and error control information may be received at the memory device via a sideband channel and corresponding pin. For example, a set of bits received via the pin may include a subset of error control bits and a subset of metadata bits. Circuitry at the memory device may receive the set of bits via the pin and may identify metadata information and error control information within the set of bits. The circuitry may route the metadata information to a corresponding subset of memory cells and the error control information to an error control circuit, where the error control circuit may route the error control information to a corresponding subset of memory cells.

公开(公告)号：WO2022120323A1

公开(公告)日：2022-06-09

申请号：PCT/US2021/072579

申请日：2021-11-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KINSLEY, Thomas, H. ,  CHOI, Baekkyu ,  BADRIEH, Fuad

IPC: G06F1/3234 ,  G06F1/3296 ,  G11C11/4074

Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.