公开(公告)号：WO2010085560A1

公开(公告)日：2010-07-29

申请号：PCT/US2010/021652

申请日：2010-01-21

Applicant: QUALCOMM INCORPORATED ,  GARG, Manish ,  CHAI, Chiaming ,  PHAN, Michael, Thai Thanh

Inventor： GARG, Manish ,  CHAI, Chiaming ,  PHAN, Michael, Thai Thanh

IPC: G11C8/08 ,  G11C11/408 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/08

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract translation: 存储单元包括存储元件，耦合到存储元件的写入电路和耦合到存储元件的读取电路。 使用较厚的功能栅极氧化物制造存储元件的至少一部分和写入电路的至少一部分，并且使用更薄的功能栅极氧化物制造读取电路的至少一部分。

公开(公告)号：WO2011116316A2

公开(公告)日：2011-09-22

申请号：PCT/US2011029046

申请日：2011-03-18

Applicant: QUALCOMM INC ,  PHAN MICHAEL THAITHANH ,  CHAI CHIAMING ,  GARG MANISH

Inventor： PHAN MICHAEL THAITHANH ,  CHAI CHIAMING ,  GARG MANISH

IPC: G11C7/06

CPC classification number: G11C7/02 ,  G11C7/065

Abstract: A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.

Abstract translation: 实现读出放大器电路以抑制米勒效应电容耦合。 放大器电路包括具有第一输入，第一输出空隙节点，第二输入，第二输出空隙节点，用于启用或禁用差分放大器的第三输入以及具有均衡器电路的差分放大器电路，所述均衡器电路耦合在第一输出 插页式节点和第二个输出插页式节点。 该放大器电路还包括具有耦合到第一输出间隙节点的第一锁存器输入，耦合到第二输出间隙节点的第二锁存器输入，第一锁存器输出和第二锁存器输出的交叉耦合锁存器电路，其中在第一 第一锁存器输出和第二锁存器输出被预充电时，差分放大器电路被禁止，并且均衡器电路被启用以抑制感测放大器输入端上的米勒效应电容耦合。

公开(公告)号：WO2008064172A3

公开(公告)日：2009-01-08

申请号：PCT/US2007085129

申请日：2007-11-19

Applicant: QUALCOMM INC ,  CHAI CHIAMING ,  HOFF DAVID PAUL ,  MARTZLOFF JASON PHILIP ,  PHAN MICHAEL THAITHANH ,  VARMA MANJU RATHNA

Inventor： CHAI CHIAMING ,  HOFF DAVID PAUL ,  MARTZLOFF JASON PHILIP ,  PHAN MICHAEL THAITHANH ,  VARMA MANJU RATHNA

IPC: H01L21/8239 ,  G11C15/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L27/105

CPC classification number: H01L27/105 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04 ,  H01L21/8221 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1052

Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells (710, 720, 730, 740) in which each adjacent CAM cell is rotated 180 relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance. The first and second CAM cells may be vertically stacked.

Abstract translation: 公开了内容可寻址存储器（CAM）。 CAM具有第一和第二CAM单元（710,720,730,740），其中每个相邻的CAM单元相对于其邻居旋转180°，这提供了具有整体匹配的CAM阵列单元和RAM阵列单元行高度的紧凑的物理布置。 此外，交错集合方案可以应用于CAM单元，以提供比较信号的降低的路由以及降低的寄生电容。 第一和第二CAM单元可以垂直堆叠。

公开(公告)号：WO2009003120A1

公开(公告)日：2008-12-31

申请号：PCT/US2008/068395

申请日：2008-06-26

Applicant: QUALCOMM INCORPORATED ,  GE, Shaoping ,  CHAI, Chiaming ,  FISCHER, Jeffery Herbert

Inventor： GE, Shaoping ,  CHAI, Chiaming ,  FISCHER, Jeffery Herbert

IPC: H03K5/1534 ,  G01R29/027

CPC classification number: H03K5/1534 ,  H03K19/19

Abstract: A number of logic state catching circuits (200) are described which use a logic circuit (204) with a first input (210), a second input, (232) and an output. The logic circuit (204) is configured to respond to a change in state of a data value coupled to the first input (210) causing a representative value of the data „ value to be generated on the output(212). The second input (232) receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element (206) is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input (232). A reset element (208) is configured to respond to a change in state of a clock input (230)by resetting the latching element. (206)

Abstract translation: 描述了使用具有第一输入（210），第二输入（232）和输出的逻辑电路（204）的多个逻辑状态捕捉电路（200）。 逻辑电路（204）被配置为响应耦合到第一输入（210）的数据值的状态变化，导致在输出（212）上产生数据“值的代表值”，第二输入 232）接收数据值的锁存版本，以在数据值已经返回到其原始状态之后将输出的代表值保持在该状态。锁存元件（206）被配置为通过锁存来响应数据值的状态改变 数据值并将锁存的数据值版本耦合到第二输入端（232），复位元件（208）被配置为通过复位锁存元件来响应时钟输入（230）的状态改变（ 206）

公开(公告)号：WO2011081951A1

公开(公告)日：2011-07-07

申请号：PCT/US2010/060361

申请日：2010-12-14

Applicant: QUALCOMM INCORPORATED ,  GARG, Manish ,  CHAI, Chiaming ,  BRIDGES, Jeffrey Todd

Inventor： GARG, Manish ,  CHAI, Chiaming ,  BRIDGES, Jeffrey Todd

IPC: H03K3/03 ,  H03K5/00

CPC classification number: H03K3/0315 ,  H03K2005/00058 ,  H03K2005/00215

Abstract: Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).

Abstract translation: 公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。 在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。 时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。 反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。 输入信号可用于向功能电路提供时钟信号。

公开(公告)号：WO2010077776A1

公开(公告)日：2010-07-08

申请号：PCT/US2009/067657

申请日：2009-12-11

Applicant: QUALCOMM Incorporated ,  CHAI, Chiaming ,  LILES, Stephen Edward

Inventor： CHAI, Chiaming ,  LILES, Stephen Edward

IPC: G11C7/08 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C7/22

CPC classification number: G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419

Abstract: Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.

Abstract translation: 公开了包括信号路径的自整定或定时在多个电压域中提供的电路和方法。 在电路中提供多个路径。 每个路径遍及多个电压域的一部分，其可以包括多个电压域的任何数量或组合。 每个路径具有响应于多个电压域中的至少一个的延迟。 延迟电路被提供并被配置为产生与多个路径中的延迟相关的延迟输出。 以这种方式，延迟电路的延迟输出根据多个路径中的延迟进行自调谐或调整。 该自整定可以特别适合于控制相对于第二信号路径的第一信号路径的延迟，其中路径中的延迟在操作期间可以相对于彼此而变化。

公开(公告)号：WO2008064172A2

公开(公告)日：2008-05-29

申请号：PCT/US2007/085129

申请日：2007-11-19

Applicant: QUALCOMM Incorporated ,  CHAI, Chiaming ,  HOFF, David, Paul ,  MARTZLOFF, Jason, Philip ,  PHAN, Michael, Thaithanh ,  VARMA, Manju, Rathna

Inventor： CHAI, Chiaming ,  HOFF, David, Paul ,  MARTZLOFF, Jason, Philip ,  PHAN, Michael, Thaithanh ,  VARMA, Manju, Rathna

IPC: H01L21/8239 ,  H01L27/02 ,  H01L27/105 ,  G11C15/04

CPC classification number: H01L27/105 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04 ,  H01L21/8221 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1052

Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.

Abstract translation: 公开了内容可寻址存储器（CAM）。 CAM具有第一和第二CAM单元，其中每个相邻的CAM单元相对于其邻居旋转180°，这提供了具有整体匹配的CAM阵列单元和RAM阵列单元行高度的紧凑的物理布置。 此外，交错集合方案可以应用于CAM单元，以提供比较信号的降低的路由以及降低的寄生电容。

公开(公告)号：WO2007051204A1

公开(公告)日：2007-05-03

申请号：PCT/US2006/060370

申请日：2006-10-30

Applicant: QUALCOMM INCORPORATED ,  PHAN, Michael, ThaiThanh ,  CHAI, Chiaming ,  BRIDGES, Jeffrey, Todd ,  FISCHER, Jeffrey, Herbert

Inventor： PHAN, Michael, ThaiThanh ,  CHAI, Chiaming ,  BRIDGES, Jeffrey, Todd ,  FISCHER, Jeffrey, Herbert

IPC: G11C15/04

CPC classification number: G11C15/00 ,  G11C8/12 ,  G11C15/04

Abstract: A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.

Abstract translation: CAM组在功能上划分为两个或更多个子行，不复制CAM驱动电路，禁止该组中的所有匹配线放电电路，并且选择性地使得放电电路在包含子行的条目中使能。 至少一个选择性致动的切换电路插入在子组的放电电路中的每个放电比较器的虚拟接地节点和电路接地之间。 当开关电路处于非导通状态时，虚拟接地节点保持在足够高于电路接地的电压电平，以防止在CAM访问时间内放电连接的匹配线。 当开关电路处于导通状态时，虚拟接地节点被拉到电路接地，并且连接的匹配线可能被误比较地放电。 可以从地址位解码的控制信号被分配给切换电路以定义CAM子库。

公开(公告)号：WO2011127023A1

公开(公告)日：2011-10-13

申请号：PCT/US2011/031198

申请日：2011-04-05

Applicant: QUALCOMM INCORPORATED ,  LILES, Stephen Edward ,  CHAI, Chiaming ,  MAMILETI, Lakshmikant

Inventor： LILES, Stephen Edward ,  CHAI, Chiaming ,  MAMILETI, Lakshmikant

IPC: H03K3/356 ,  G11C11/419

CPC classification number: H03K3/356182 ,  H03K3/356113

Abstract: Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.

Abstract translation: 公开了动态电压电平移位电路，系统和方法。 电平移位电路包括用于接受要移位的第一离散电压电平的输入端，耦合到输入端和第二离散电压电平的电平移位部分，具有使能输入并耦合到电平转换部分的使能部分和 输出。 电平移位电路被配置为将在第一离散电压电平处的数据输入转换成第二离散电压电平。 使能部分被配置为基于使能输入，选择性地将输出的第二离散电压电平或电平移位部分的至少一部分从输出分离。

公开(公告)号：WO2011116316A3

公开(公告)日：2011-09-22

申请号：PCT/US2011/029046

申请日：2011-03-18

Applicant: QUALCOMM INCORPORATED ,  PHAN, Michael ThaiThanh ,  CHAI, Chiaming ,  GARG, Manish

Inventor： PHAN, Michael ThaiThanh ,  CHAI, Chiaming ,  GARG, Manish

IPC: G11C7/06

Abstract: A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.