公开(公告)号：WO2018044383A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/039323

申请日：2017-06-26

申请人： QUALCOMM INCORPORATED

发明人： PARK, Dongmin ,  PARK, Jong Min ,  LEUNG, Lai Kan

IPC分类号： H03K3/356

CPC分类号： H03K19/018507 ,  H03K3/356104 ,  H03K3/356113

摘要： A level-shifter is provided in which the devices may all be sized approximately the same yet a known startup state is provided at power-up by forming the level-shifter using a one-sided NMOS latch. The one-sided NMOS latch is powered through a pair of head-switch transistors. A pair of pull-down transistors function to flip a binary state for the one-sided NMOS latch.

摘要翻译： 提供了一种电平移位器，其中器件的大小可以全部大致相同，但是通过使用单侧NMOS锁存器形成电平移位器而在加电时提供已知的启动状态。 单侧NMOS锁存器通过一对头部开关晶体管供电。 一对下拉晶体管用于翻转单边NMOS锁存器的二进制状态。

公开(公告)号：WO2015187482A8

公开(公告)日：2016-01-28

申请号：PCT/US2015033155

申请日：2015-05-29

申请人： UNIV YALE

发明人： SUN XIAO ,  MA TSO-PING

IPC分类号： H03K17/06

CPC分类号： H03K19/01714 ,  H03K3/356113 ,  H03K19/094

摘要： Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

摘要翻译： 本公开的示例性实施例涉及自举模块和利用自举模块补偿弱高条件的逻辑电路。 可以使用具有与在逻辑电路中使用的晶体管的通道类型相同的单通道类型的晶体管来实现自举模块，使得可以在解决这种单极电路的弱高问题的同时实现真正的单极电路。

公开(公告)号：WO2012115900A3

公开(公告)日：2014-04-17

申请号：PCT/US2012025803

申请日：2012-02-20

申请人： DEERE & CO ,  CLEMENTS NEAL D

发明人： CLEMENTS NEAL D

IPC分类号： G05F3/16

CPC分类号： H03K19/01 ,  H03K3/356113 ,  H03K17/164 ,  H03K19/0175

摘要： A driver circuit (10) for controlling a semiconductor power switch (Q7) comprises a first power driver transistor (QS) and a second power driver transistor (Q5) complementary to the first power driver transistor (08). Both power driver transistors (Q5, Q6) have an output terminal connected to an input terminal (34) of the semiconductor power switch (Q7). An input terminal of the second power driver transistor (Q5) is connected to a half bridge circuit comprising a; first pre-driver transistor (Q3) and a second pre-driver transistor (04) complementary to the first pre-driver transistor

摘要翻译： 用于控制半导体功率开关（Q7）的驱动电路（10）包括与第一功率驱动晶体管（08）互补的第一功率驱动晶体管（QS）和第二功率驱动晶体管（Q5）。 两个功率驱动晶体管（Q5，Q6）都具有连接到半导体功率开关（Q7）的输入端子（34）的输出端子。 第二功率驱动晶体管（Q5）的输入端连接到包括a的半桥电路; 第一预驱动晶体管（Q3）和与第一预驱动晶体管

公开(公告)号：WO2012115900A2

公开(公告)日：2012-08-30

申请号：PCT/US2012/025803

申请日：2012-02-20

申请人： DEERE & COMPANY ,  CLEMENTS, Neal, D.

发明人： CLEMENTS, Neal, D.

IPC分类号： H03K3/00

CPC分类号： H03K19/01 ,  H03K3/356113 ,  H03K17/164 ,  H03K19/0175

摘要： A driver circuit (10) for controlling a semiconductor power switch (Q7) comprises a first power driver transistor (QS) and a second power driver transistor (Q5) complementary to the first power driver transistor (08). Both power driver transistors (Q5, Q6) have an output terminal connected to an input terminal {34} of the semiconductor power switch (Q7). An input terminal of the second power driver transistor (Q5) is connected to a half bridge circuit comprising a; first pre-driver transistor (Q3) and a second pre-driver transistor (04) complementary to the first pre-driver transistor

摘要翻译： 用于控制半导体功率开关（Q7）的驱动电路（10）包括与第一功率驱动晶体管（08）互补的第一功率驱动晶体管（QS）和第二功率驱动晶体管（Q5）。 两个功率驱动晶体管（Q5，Q6）都具有连接到半导体功率开关（Q7）的输入端子（34）的输出端子。 第二功率驱动晶体管（Q5）的输入端连接到包括a的半桥电路; 第一预驱动晶体管（Q3）和与第一预驱动晶体管

公开(公告)号：WO2011132023A1

公开(公告)日：2011-10-27

申请号：PCT/IB2010/051767

申请日：2010-04-22

申请人： FREESCALE SEMICONDUCTOR, INC. ,  SOFER, Sergey ,  PRIEL, Michael ,  TZYTKIN, Dov

发明人： SOFER, Sergey ,  PRIEL, Michael ,  TZYTKIN, Dov

IPC分类号： H03K19/0185

CPC分类号： H03K3/356113

摘要： A voltage level shifter (10) for translating a binary input signal (IN_L) representing a binary sequence to a binary output signal (OUT_H) representing the same binary sequence. The voltage level shifter comprises an input port (12) for receiving the binary input signal as an input voltage varying between a first input voltage level (VSS) and a second input voltage level (VDD). An output port (14) is connected to a node (16) for outputting the binary output signal as an output voltage varying between a first output voltage level (VBB) and a second output voltage level (VPP). A supply voltage node (18) connectable to a voltage supply, can provide the second output voltage level (VPP). A first switch (22) is arranged to couple the supply voltage node (18) to the node (16) and to decouple the supply voltage node (18) from the node (16) based on a voltage at the node (16). A feedback voltage loop (40) is connected to the node (16) for providing a feedback voltage (VFB) based on the voltage at the node (16). A second switch (42) is connected to the feedback voltage loop and arranged to couple the input port (12) to the node (16) based on a voltage at the input port and the feedback voltage (VFB). A decoupler and a voltage shifting method are also disclosed.

摘要翻译： 一种用于将表示二进制序列的二进制输入信号（IN_L）转换为表示相同二进制序列的二进制输出信号（OUT_H）的电压电平移位器（10）。 电压电平移位器包括用于接收二进制输入信号作为在第一输入电压电平（VSS）和第二输入电压电平（VDD）之间变化的输入电压的输入端口（12）。 输出端口（14）连接到节点（16），用于输出二进制输出信号作为在第一输出电压电平（VBB）和第二输出电压电平（VPP）之间变化的输出电压。 可连接到电源的电源电压节点（18）可以提供第二输出电压电平（VPP）。 第一开关（22）布置成将电源电压节点（18）耦合到节点（16），并且基于节点（16）处的电压将电源电压节点（18）与节点（16）去耦。 反馈电压回路（40）连接到节点（16），用于基于节点（16）处的电压提供反馈电压（VFB）。 第二开关（42）连接到反馈电压回路并且被布置为基于输入端口处的电压和反馈电压（VFB）将输入端口（12）耦合到节点（16）。 还公开了解耦器和电压移位方法。

公开(公告)号：WO2009027468A2

公开(公告)日：2009-03-05

申请号：PCT/EP2008/061304

申请日：2008-08-28

申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH ,  ARNOLD, Matthias ,  GERBER, Johannes ,  RUCK, Bernhard Wolfgang

发明人： ARNOLD, Matthias ,  GERBER, Johannes ,  RUCK, Bernhard Wolfgang

IPC分类号： H03K3/356

CPC分类号： H03K3/356113

摘要： An electronic device with a supply voltage level converter converts a signal from a first low supply voltage level to a second high supply voltage level includes; a first pair of cross coupled MOS transistors compliant with the second supply voltage level, each having a source coupled to the second supply voltage level and providing complementary output signals at respective drains; driven by a second pair of common gate MOS transistors compliant with the second supply voltage; driven by a third pair of common gate MOS transistors compliant with the first voltage level; and driven by first and second inverters coupled in a chain and supplied by the first supply voltage level, each having an output connected to the source of a transistor in a third pair.

摘要翻译： 具有电源电压电平转换器的电子设备将信号从第一低电源电压电平转换为第二高电源电压电平，包括： 第一对交叉耦合的MOS晶体管，符合第二电源电压电平，每个具有耦合到第二电源电压电平的源极和在各自的漏极提供互补的输出信号; 由符合第二电源电压的第二对共栅MOS晶体管驱动; 由符合第一电压电平的第三对公共栅极MOS晶体管驱动; 并由第一和第二反相器驱动，第一和第二反相器耦合在一个链中并由第一电源电压电平提供，每个具有连接到第三对晶体管的源极的输出。

公开(公告)号：WO2009005941A3

公开(公告)日：2009-02-26

申请号：PCT/US2008065843

申请日：2008-06-05

申请人： MICRON TECHNOLOGY INC ,  HOLLIS TIMOTHY M

发明人： HOLLIS TIMOTHY M

IPC分类号： G11C11/407

CPC分类号： H03K3/356113 ,  H03K5/082 ,  H04L25/03057

摘要： Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one- half-rate clocked DFE circuit utilizes two input data paths, which are respectively activated on rising and falling edges of an associated half-rate clock. Each of the input data paths has a pair of comparators with differing reference voltage levels. The comparators in each input data path output to a multiplexer, which picks between the two comparator outputs depending on the logic level of the previously received bit. The output of each input data path is sent as a control input to the multiplexer of the other data path. Thus, the results from previously- detected bits affect which comparator's output is passed to the output of the circuit, even though the synchronizing clock is half the frequency of the data. A quarter-rate DFE circuit is also disclosed which operates similarly.

摘要翻译： 公开了用于与数据信号相比频率较小的分数速率时钟的判决反馈均衡（DFE）电路。 例如，一个半速时钟的DFE电路使用两个输入数据路径，分别在相关的半速时钟的上升沿和下降沿激活。 每个输入数据路径具有一对具有不同参考电压电平的比较器。 每个输入数据路径中的比较器输出到多路复用器，它根据先前接收的位的逻辑电平在两个比较器输出之间进行选择。 每个输入数据路径的输出作为控制输入发送到另一数据路径的多路复用器。 因此，即使同步时钟是数据频率的一半，先前检测到的位的结果影响哪个比较器的输出传递到电路的输出。 还公开了类似地操作的四分之一速率DFE电路。

公开(公告)号：WO2008101548A1

公开(公告)日：2008-08-28

申请号：PCT/EP2007/051731

申请日：2007-02-22

申请人： MUETA B.V. ,  SEESINK, Peter

发明人： SEESINK, Peter

IPC分类号： H03F3/217

CPC分类号： H03F3/217 ,  H03K3/356113 ,  H03K17/18 ,  H03K17/6871 ,  H03K19/00361 ,  H03K19/017509

摘要： A level shift circuit for transferring an input signal (60, 90) referenced to a first reference voltage (V sshs , V ssls ) to an output signal (65, 66, 95, 96) referenced to a second reference voltage (V ssls , V sshs ). The circuit comprises a first pull-up transistor (42), a first shielding transistor (43), and a first pull-down transistor (44) connected in series between the first reference voltage and the second reference voltage, and a second pull-up transistor (45), a second shielding transistor (46), and a second pull-down transistor (47) connected in series between the first reference voltage and the second reference voltage. The first pull-up transistor is controlled by the input signal, and the second pull-up transistor controlled by an inverted signal derived from the input signal. The gate terminals of the first and second shielding transistors are connected through gate series resistors (50, 51) to a third voltage (V ddls ) having a fixed difference from the second reference voltage. The output signal is taken from a first node (62) between the first shielding transistor and the first pull-down transistor or a second node (64) between the second shielding transistor and the second pull-down transistor.

摘要翻译： 一种电平移位电路，用于将参考第一基准电压（V S S S S S S S S S S S S S S S H S）的输入信号（60,90）传送到输出信号（65,66， 参考第二参考电压（V SUB，S S S S S S S S S S S S S S S S S s）。 该电路包括串联连接在第一参考电压和第二参考电压之间的第一上拉晶体管（42），第一屏蔽晶体管（43）和第一下拉晶体管（44） 上拉晶体管（45），第二屏蔽晶体管（46）和串联连接在第一参考电压和第二参考电压之间的第二下拉晶体管（47）。 第一上拉晶体管由输入信号控制，第二上拉晶体管由从输入信号导出的反相信号控制。 第一和第二屏蔽晶体管的栅极端子通过栅极串联电阻器（50,51）连接到与第二参考电压具有固定差值的第三电压（V SUB）。 输出信号取自第一屏蔽晶体管和第一下拉晶体管之间的第一节点（62）或第二屏蔽晶体管和第二下拉晶体管之间的第二节点（64）。

公开(公告)号：WO2007116378A3

公开(公告)日：2008-03-27

申请号：PCT/IB2007051296

申请日：2007-04-11

申请人： KONINKL PHILIPS ELECTRONICS NV ,  NEDALGI DHARMARAY M

发明人： NEDALGI DHARMARAY M

IPC分类号： H03K17/10 ,  H03K19/0185

CPC分类号： H03K19/018521 ,  H03K3/356113 ,  H03K19/00315

摘要： An electronic circuit is provided comprising an input (V IN ) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M1) is coupled between the voltage (VSS) and a first node (tn). The second transistor (M2) is coupled between a second node (tp) and the output (V OUT ). The third transistor (M3) is coupled between the first node (tn) and the output (V OUT ). The fourth transistor (M4) is coupled between the supply voltage (VDD) and the second node (tp). A first reference voltage generating unit (RC) receives the voltage at the first node (tn) and the voltage (VSS) as input, and its output is coupled to the gate of the second transistor (M2). A second reference voltage generating unit (RD) receives the supply voltage (VDD) and the voltage of the second node (tp) as input, and its output is coupled to the gate of the third transistor (M3). The first and second reference voltage generating units (RD, RC) generate a reference voltage according to at least one of the logic states of the first, second, third or fourth transistor (M1-M4) .

摘要翻译： 提供一种电子电路，其包括用于将第一电压域的电路耦合到电子电路的输入端（V IN IN IN）以及耦合在电源电压（VDD）之间的第一，第二，第三和第四晶体管 ）和电压（VSS）。 第三晶体管（M1）耦合在电压（VSS）和第一节点（tn）之间。 第二晶体管（M2）耦合在第二节点（tp）和输出端（V OUT OUT）之间。 第三晶体管（M3）耦合在第一节点（tn）和输出端（V OUT OUT）之间。 第四晶体管（M4）耦合在电源电压（VDD）和第二节点（tp）之间。 第一参考电压产生单元（RC）接收第一节点（tn）处的电压和作为输入的电压（VSS），并且其输出耦合到第二晶体管（M2）的栅极。 第二参考电压产生单元（RD）接收电源电压（VDD）和第二节点（tp）的电压作为输入，并且其输出耦合到第三晶体管（M3）的栅极。 第一和第二参考电压产生单元（RD，RC）根据第一，第二，第三或第四晶体管（M1-M4）的逻辑状态中的至少一个产生参考电压。

公开(公告)号：WO2004032323A2

公开(公告)日：2004-04-15

申请号：PCT/DE0303264

申请日：2003-09-25

申请人： ALPHA MICROELECTRONICS GMBH ,  HEINZ STEFFEN ,  EBEST GUNTER ,  DIETRICH JUERGEN ,  KNOPKE JUERGEN ,  MIESCH WOLFGANG

发明人： HEINZ STEFFEN ,  EBEST GUNTER ,  DIETRICH JUERGEN ,  KNOPKE JUERGEN ,  MIESCH WOLFGANG

IPC分类号： H03K3/012 ,  H03K3/356 ,  H03K19/0185 ,  H03K17/00

CPC分类号： H03K3/356113 ,  H03K3/012 ,  H03K19/018521

摘要： The invention relates to circuit arrangements for bridging high voltages using a switching signal as a dynamic voltage level shifter. Said arrangements are characterised in particular in that switching signal sequences can be processed or provided at different voltage levels. A fundamental advantage of this is that any technology for integrated high-voltage circuits involving any isolation method can be used to produce the inventive circuit arrangements for switching over high voltages. The circuit arrangements for switching over high voltages, also known as dynamic voltage level shifters, make available signal levels with conventional voltage levels of between 3 V and 15 V at another voltage level, using a potential differential of a few volts up to several hundred volts (depending on the technology and application used). The potential differential between the input voltage level, or voltage transmitter and the output voltage level, or voltage receiver can be either positive or negative, or can vary in intensity.

摘要翻译： 本发明涉及一种电路装置用于桥接使用切换信号作为动态电压电平移位器的高电压。 这些在特定的事实，切换信号序列可以在不同的电压电平被处理或提供区分。 甲显著优点是，与用于实现根据本发明的电路布置中的任何绝缘方法集成的高电压电路的任何技术可用于开关的高电压。 用于切换高电压，也被称为动态电压电平移位器，所述电路装置被使用，数字信号电平使用约3V之间的常规的功率电平，以15 V几伏的电位差来几百伏（取决于技术和应用） 穿上不同的电压电平。 在这种情况下，电压发射机之间的电位差被可互换地称为输入电压电平，并且被同义地称为电压接收器的输出电压电平，是正的或负的电位水平也改变。