公开(公告)号：WO2011083041A1

公开(公告)日：2011-07-14

申请号：PCT/EP2010/070366

申请日：2010-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  KUMAR, Arvind ,  CHOU, Anthony, I-Chih

Inventor： KUMAR, Arvind ,  CHOU, Anthony, I-Chih

IPC: H01L21/8247 ,  H01L27/12 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/11558 ,  H01L29/1087 ,  H01L29/78615

Abstract: A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.

Abstract translation: 提供了一种用于使用身体接触的SOI晶体管的单个多重非易失性存储器的读取晶体管及其制造方法。 非易失性随机存取存储器形成在绝缘体上硅（SOI）中。 非易失性随机存取存储器包括在SOI的硅中形成有体接触的读取场效应晶体管（FET）。 身体接触与读取FET的栅极下方的扩散区域电接触。

公开(公告)号：WO2005036641A1

公开(公告)日：2005-04-21

申请号：PCT/US2004/028878

申请日：2004-09-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHOU, Anthony, I. ,  FURUKAWA, Toshiharu ,  VAREKAMP, Patrick, R. ,  SLEIGHT, Jeffrey, W. ,  SEKIGUCHI, Akihisa

Inventor： CHOU, Anthony, I. ,  FURUKAWA, Toshiharu ,  VAREKAMP, Patrick, R. ,  SLEIGHT, Jeffrey, W. ,  SEKIGUCHI, Akihisa

IPC: H01L21/8238

CPC classification number: H01L21/28202 ,  H01L21/823842 ,  H01L21/823857

Abstract: A method of forming CMOS semiconductor (10) materials with PFET (16) and NFET (14) areas formed on a semiconductor substrate (12), covered respectively with a PFET (16) and NFET (14) gate dielectric layers composed of silicon oxide and different degrees of nitridation (18D and 18E) thereof. Provide a silicon substrate (12) with a PFET (16) area and an NFET (14) area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer (42) above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric I ayer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer (40) above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer (40) and the PFET gate dielectric layer (42) can have the same thickness.

Abstract translation: 一种用半导体衬底（12）形成的PFET（16）和NFET（14）区域形成CMOS半导体（10）材料的方法，分别覆盖由PFET（16）和NFET（14）构成的栅氧化层 和不同程度的氮化（18D和18E）。 提供具有PFET（16）区域和NFET（14）区域的硅衬底（12），并在其上形成PFET和NFET栅极氧化物层。 在PFET区域上方提供PFET栅极氧化物层的氮化，以在PFET区域上方形成PFET栅极电介质层（42），PFET栅极电介质I的第一浓度水平位于PFET区域上方。 提供NFET栅极氧化物层的氮化以在NFET区域上方形成具有与第一浓度水平不同的氮原子浓度水平的NFET栅极介电层（40）。 NFET栅极电介质层（40）和PFET栅极电介质层（42）可以具有相同的厚度。

公开(公告)号：WO2010107531A1

公开(公告)日：2010-09-23

申请号：PCT/US2010/023839

申请日：2010-02-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHOU, Anthony, I. ,  FREEMAN, Gregory, G. ,  MCSTAY, Kevin ,  NARASIMHA, Shreesh

Inventor： CHOU, Anthony, I. ,  FREEMAN, Gregory, G. ,  MCSTAY, Kevin ,  NARASIMHA, Shreesh

IPC: H01L21/33

CPC classification number: H01L21/28518 ,  H01L21/76829 ,  H01L29/66356 ,  H01L29/7391

Abstract: A gated diode structure and a method for fabricating the gated diode structure on an SOI substrate (10), uses a relaxed liner (34') that is derived from a stressed liner (34) that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner (34). The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.

Abstract translation: 栅极二极管结构和在SOI衬底（10）上制造门控二极管结构的方法使用从应力衬里（34）导出的松弛衬垫（34'），其通常在场效应的上下文中使用 晶体管与门控二极管结构同时形成。 松弛的衬垫与应力衬垫（34）的处理（例如离子注入处理）形成。 与使用反应离子蚀刻方法相比，轻松的衬垫与应力衬里相比提供了改进的门控二极管理想，没有任何门控二极管损坏，其可能发生在从选通二极管结构剥离应力衬垫的同时发生。

公开(公告)号：WO2005013348A2

公开(公告)日：2005-02-10

申请号：PCT/US2004/024595

申请日：2004-07-30

Applicant: TOKYO ELECTRON LIMITED ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  O'MEARA, David, L. ,  WAJDA, Cory ,  DIP, Anthony ,  TOELLER, Michael ,  FURUKAWA, Toshihara ,  SCHEER, Kristen ,  CALLEGARI, Alessandro ,  BUEHRER, Fred ,  ZAFAR, Sufi ,  GOUSEV, Evgeni ,  CHOU, Anthony ,  HIGGINS, Paul

Inventor： O'MEARA, David, L. ,  WAJDA, Cory ,  DIP, Anthony ,  TOELLER, Michael ,  FURUKAWA, Toshihara ,  SCHEER, Kristen ,  CALLEGARI, Alessandro ,  BUEHRER, Fred ,  ZAFAR, Sufi ,  GOUSEV, Evgeni ,  CHOU, Anthony ,  HIGGINS, Paul

IPC: H01L21/314

CPC classification number: H01L21/67098 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662

Abstract: Ultra-thin oxide and oxynitride layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide and oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in Si0 2 layers with a thickness of about 15Å, where the thickness of the Si0 2 layers varies less than about 1 Åover the substrates.

Abstract translation: 使用低压处理形成超薄氧化物和氧氮化物层，以实现衬底的自限制氧化并提供超薄氧化物和氧氮化物。 待处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层，氮化物层，高k层，或者可以缺少初始介电层。 处理可以使用间歇式处理室进行，或者使用单晶圆处理室进行。 本发明的一个实施例提供Si衬底的自限制氧化，其导致SiO 2层的厚度为约15，其中SiO 2层的厚度在基板之外变化小于约1埃。

公开(公告)号：WO2009003151A1

公开(公告)日：2008-12-31

申请号：PCT/US2008/068452

申请日：2008-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHOU, Anthony, I-Chih ,  DUNN, James, S. ,  DUFRENE, Brian, M. ,  LUMBRA, Christopher, H. ,  NARASIMHA, Shreesh ,  PUTNAM, Christopher, S. ,  RAINEY, BethAnn ,  SCHNABEL, Christopher, M.

Inventor： CHOU, Anthony, I-Chih ,  DUNN, James, S. ,  DUFRENE, Brian, M. ,  LUMBRA, Christopher, H. ,  NARASIMHA, Shreesh ,  PUTNAM, Christopher, S. ,  RAINEY, BethAnn ,  SCHNABEL, Christopher, M.

IPC: G01R31/26 ,  H01L21/00

CPC classification number: G06F17/5068 ,  G06F2217/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system, method and program product that allows multiple devices (18) to be placed between pads (12, 14, 16) such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system (58) is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system (60) for designing a plurality of device options (dl, d2, d3, d4) for a set of chip pads (12, 14, 16); a system (62) for designing a pseudo wiring layout for each of the plurality of device options; a system (64) for selecting one of the device options; a system (66) for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system (50) for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.

Abstract translation: 一种允许将多个设备（18）放置在焊盘（12,14,16）之间的系统，方法和程序产品，从而可以使用后端（BEOL）掩模改变来选择不同的设备选项。 公开了一种用于实现用于表征集成电路技术中的器件的测试现场的系统（58），并且包括：用于设计用于一组芯片焊盘的多个器件选项（d1，d2，d3，d4）的系统（60） （12,14,16）; 用于为所述多个设备选项中的每一个设计伪布线布局的系统（62） 用于选择所述设备选项之一的系统（64） 用于将所选择的设备选项的伪布线布局映射到预定设计级的系统（66） 以及用于在预定设计级别输出配置的掩模设计的系统（50），其具有为所选择的设备选项映射的布线布局。

公开(公告)号：WO2005013348A3

公开(公告)日：2005-09-22

申请号：PCT/US2004024595

申请日：2004-07-30

Applicant: TOKYO ELECTRON LTD ,  IBM ,  O'MEARA DAVID L ,  WAJDA CORY ,  DIP ANTHONY ,  TOELLER MICHAEL ,  FURUKAWA TOSHIHARA ,  SCHEER KRISTEN ,  CALLEGARI ALESSANDRO ,  BUEHRER FRED ,  ZAFAR SUFI ,  GOUSEV EVGENI ,  CHOU ANTHONY ,  HIGGINS PAUL

Inventor： O'MEARA DAVID L ,  WAJDA CORY ,  DIP ANTHONY ,  TOELLER MICHAEL ,  FURUKAWA TOSHIHARA ,  SCHEER KRISTEN ,  CALLEGARI ALESSANDRO ,  BUEHRER FRED ,  ZAFAR SUFI ,  GOUSEV EVGENI ,  CHOU ANTHONY ,  HIGGINS PAUL

IPC: H01L21/00 ,  H01L21/314 ,  H01L21/316 ,  C23C16/30 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/318

CPC classification number: H01L21/67098 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662

Abstract: Ultra-thin oxide and oxynitride layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide and oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in Si02 layers with a thickness of about 15Å, where the thickness of the Si02 layers varies less than about 1 Åover the substrates.

Abstract translation: 使用低压处理形成超薄氧化物和氮氧化物层以实现衬底的自限氧化并提供超薄氧化物和氮氧化物。 待处理的衬底可以包含诸如氧化物层，氮氧化物层，氮化物层，高k层的初始电介质层，或者可替代地可以缺少初始电介质层。 该处理可以使用批量式处理室或者使用单晶片处理室来进行。 本发明的一个实施方案提供了Si-衬底的自限氧化，其导致厚度为约的SiO 2层，其中SiO 2层的厚度在衬底上的变化小于约1。