Abstract:
A high-speed router backplane is disclosed. The disclosed construction and layout techniques enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that use signaling across the backplane at trace speeds of 2.5 Gbps or greater. Specific ranges of differential trace geometry characteristics, with significant single-ended coupling to adjacent ground planes, have been found to provide the parameters needed for such signaling. New trace routing and layering techniques also help in the realization of a backplane embodiment containing roughly 600 operable high-speed differential pairs, while also providing sufficient electromagnetic interference management to allow power distribution to occur within the same backplane.
Abstract:
In one embodiment, a hybrid backplane coding scheme transmits data using lengthy sequences of scrambled data, separated by 8b/ 10b control character sequences that prepare the receiver for the next scrambled sequence and permit realignment if necessary. Several lanes are coded separately in this manner, and then multiplexed on a common channel. Alignment sequences in the control character sequences, as well as scrambler seeds, are set to avoid synchronization of patterns generated among all lanes, which would tend to confuse a receiving serdes and/or phase-locked loop that recovers timing from the multiplexed scrambled signals.
Abstract:
In one embodiment, a hybrid backplane coding scheme transmits data using lengthy sequences of scrambled data, separated by 8b/ 10b control character sequences that prepare the receiver for the next scrambled sequence and permit realignment if necessary. Several lanes are coded separately in this manner, and then multiplexed on a common channel. Alignment sequences in the control character sequences, as well as scrambler seeds, are set to avoid synchronization of patterns generated among all lanes, which would tend to confuse a receiving serdes and/or phase-locked loop that recovers timing from the multiplexed scrambled signals.
Abstract:
A high-speed, high-power modular router is disclosed. As opposed to conventional designs using optical backplane signaling and/or bus bars for power distribution, the disclosed embodiments combine high-power, low-noise power distribution with high-speed signal routing in a common backplane. Disclosed backplane features allow backplane signaling at 2.5 Gbps or greater on electrical differential pairs distributed on multiple high-speed signaling layers. Relatively thick power distribution layers are embedded within the backplane, shielded from the high-speed signaling layers by digital ground layers and other shielding features. A router using such a backplane provides a level of performance and economy that is believed to be unattainable by the prior art.
Abstract:
A packet network device includes a route processor that operates to maintain one or more forwarding tables and it includes one or more line cards that operate to process information received by the packet network device from the network and to forward the information to its correct destination. The route processor also operates to identify which incoming prefixes can be used to update the forwarding tables or to identify prefixes stored in the packet network device that can be redistributed from one network protocol to another network protocol running on the route processor. A table management function running on the route processor operates to identify the best match between an incoming prefix and information included in policy statement associated with both an ordered prefix-list and a radix tree structure.
Abstract:
A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. Thru- holes are used to connect the differential signal pairs to external components. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. At least some of the thru-holes and vias are drilled to reduce an electrically conductive stub length portion of the hole. The drilled portion of a hole includes a transition from a first profile to a second profile to reduce radio frequency reflections from the end of the drilled hole.
Abstract:
A high-speed router backplane, and method for its fabrication, are disclosed. The backplane uses differential signaling trace pairs on multiple high-speed signaling layers, the high-speed signaling layers separated by ground planes. Plated signaling thru-holes connect the trace pairs to the board surface for connection to external components. The signaling thru-holes pass through clearances in each ground plane. At selected ground planes, a conductive pad is patterned within each high-speed signaling thru-hole clearance, the pad slightly larger than the thru-hole diameter. The pads affect the impedance characteristics of the thru-holes, thus providing a better impedance match to the differential trace pairs, reducing signal reflections, and improving the ability to signal across the backplane at high speeds.
Abstract:
A packet network device includes a control module, one or more line cards each one or which includes a plurality of ingress and egress ports, and each of the ingress and egress ports are connected to external network links. The line cards maintain forwarding tables and include functionality that employs information in the forwarding tables to determine how incoming packets of information should be forwarded. The control module includes functionality that operates to learn reachability information about other devices connected to the network that are and to use this reachability information to update forwarding tables maintained on the line cards. The control module also includes an enhance ARP functionality that operates in cooperation with standard ARP functionality and other network protocols included on the control module to diminish the amount of data lost in the event that a link connected to one of the egress ports fails.
Abstract:
The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.
Abstract:
A high-speed router backplane is disclosed. Because of the large number of high-speed conductive traces present in such a backplane, electromagnetic interference (EMI) can be a serious issue. And because such a router consumes significant amounts of power, some provision must exist (e.g., bus bars in the prior art) within the router for distributing power to the router components. In preferred embodiments, power distribution is accomplished using relatively thick (e.g., three- or four-ounce copper) power distribution planes within the same backplane used for high-speed signaling. To shield these planes from EMI, they are preferably placed near the center of the material stack, shielded from the signaling layers by adjacent digital ground planes. Also, where two power supply planes exist, the power supply planes are placed adjacent, further shielded by their respective power return planes. Each power distribution plane can also include a conductive guard ring to shield that plane from EMI injected at the board edges. And where the backplane includes both high-speed and lower speed signaling traces, at least some lower speed signaling traces are placed on signaling layers, designated as low-speed, that are closest to the power distribution planes.