Abstract:
A process for fabricating a circuit board includes: providing a substrate (10) including a first electrically conductive core (12) having a first insulating coating (14) on a first side and a second insulating coating (16) on a second side, forming an opening (22) in the first and second insulating coatings and the first electrically conductive core, exposing an edge (24) of the conductive core within the opening, and electrodepositing a third insulating material (28) on the exposed edge of the first electrically conductive core. A circuit board fabricated using the process is also provided.
Abstract:
Die Erfindung geht aus von einem integrierten elektronischen Bauteil mit wenigstens einer Leiterplatte (10), mit wenigstens einem auf der Leiterplatte (10) angeordneten elektronischen Leistungsbauelement (11 ) sowie einem Gehäuse, das die Leiterplatte (10) wenigstens teilweise umgibt. Es wird vorgeschlagen, dass die Leiterplatte (10) wenigstens eine Innenlage (12) aus einem wärmeleitfähigem Material aufweist. Die Erfindung betrifft ferner eine Kühlvorrichtung für ein integriertes elektronisches Bauteil (17) mit wenigstens einer Leiterplatte (10), mit wenigstens einem auf der Leiterplatte (10) angeordneten elektronischen Leistungsbauelement (11 ) sowie einem Gehäuse.
Abstract:
The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.
Abstract:
A high-speed router backplane is disclosed. Because of the large number of high-speed conductive traces present in such a backplane, electromagnetic interference (EMI) can be a serious issue. And because such a router consumes significant amounts of power, some provision must exist (e.g., bus bars in the prior art) within the router for distributing power to the router components. In preferred embodiments, power distribution is accomplished using relatively thick (e.g., three- or four-ounce copper) power distribution planes within the same backplane used for high-speed signaling. To shield these planes from EMI, they are preferably placed near the center of the material stack, shielded from the signaling layers by adjacent digital ground planes. Also, where two power supply planes exist, the power supply planes are placed adjacent, further shielded by their respective power return planes. Each power distribution plane can also include a conductive guard ring to shield that plane from EMI injected at the board edges. And where the backplane includes both high-speed and lower speed signaling traces, at least some lower speed signaling traces are placed on signaling layers, designated as low-speed, that are closest to the power distribution planes.
Abstract:
The present invention provides a heat spreading connector suitable for use with electronic components including those using land grid arrays and pin grid arrays and a method for its use. The connector of the present invention includes a housing (26) at least one dielectric layer (50) and contacts (24) in contact with the thermally conductive layer.
Abstract:
According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer (11,11') and a prefabricated product (1) are placed between two perforation dies (21,23) or a support and a perforation die. The prefabricated product (1) is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die (21,22), perforation tips of the perforation dies forming microvias for contacting the structures. A surface of the dielectric layer (11,11') or the prefabricated product (1) is configurated or coated to in a manner that the prefabricated product (1) and the dielectric layer (11,11') stick to each other after the pressure has been applied.
Abstract:
An integrated double sided metal supported display device has a green tape stack on both sides of the metal support. The green tape stacks incorporate circuitry and conductor filled vias to access the circuitry electrically on each green tape layer. The metal support has a plurality of openings to access both of the green tape stacks. These openings are made by forming the openings in the metal support, filling them with a dielectric that has a thermal coefficient of expansion close to that of the metal support, forming an opening in the dielectric and filling the opening with a conductive ink.