公开(公告)号：WO2012145117A3

公开(公告)日：2013-01-17

申请号：PCT/US2012029893

申请日：2012-03-21

Applicant: RAMBUS INC ,  GIOVANNINI THOMAS J ,  BEST SCOTT C ,  LUO LEI ,  SHAEFFER IAN

Inventor： GIOVANNINI THOMAS J ,  BEST SCOTT C ,  LUO LEI ,  SHAEFFER IAN

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract translation: 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

公开(公告)号：WO2012145117A2

公开(公告)日：2012-10-26

申请号：PCT/US2012/029893

申请日：2012-03-21

Applicant: RAMBUS INC. ,  GIOVANNINI, Thomas, J. ,  BEST, Scott, C. ,  LUO, Lei ,  SHAEFFER, Ian

Inventor： GIOVANNINI, Thomas, J. ,  BEST, Scott, C. ,  LUO, Lei ,  SHAEFFER, Ian

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract translation: 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

公开(公告)号：WO2009002646A1

公开(公告)日：2008-12-31

申请号：PCT/US2008/064901

申请日：2008-05-27

Applicant: INTEL CORPORATION ,  NAHAPETIAN, Gevorg ,  CHEN, Chih-Hao ,  GIOVANNINI, Thomas, J.

Inventor： NAHAPETIAN, Gevorg ,  CHEN, Chih-Hao ,  GIOVANNINI, Thomas, J.

IPC: G02F1/035

CPC classification number: H04B10/50575 ,  H04B10/505

Abstract: In one embodiment, the present invention includes a controller coupled to an optical modulator to receive a dither signal, determine a difference between the dither signal and a previous dither signal, determine a derivative of the difference with respect to a bias voltage difference between first and second bias voltages, and control a bias voltage for the optical modulator based on the derivative. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括耦合到光调制器以接收抖动信号的控制器，确定抖动信号和先前抖动信号之间的差异，确定相对于第一和第 第二偏置电压，并且基于导数来控制用于光调制器的偏置电压。 描述和要求保护其他实施例。

公开(公告)号：WO2012012054A1

公开(公告)日：2012-01-26

申请号：PCT/US2011/040690

申请日：2011-06-16

Applicant: RAMBUS INC. ,  SHAEFFER, Ian ,  GIOVANNINI, Thomas J.

Inventor： SHAEFFER, Ian ,  GIOVANNINI, Thomas J.

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G06F13/1689 ,  G06F12/00 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/2254

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

Abstract translation: 描述了用于存储器控制器，存储器件和系统的操作的装置和方法。 在操作期间，存储器控制器发送读取命令，该命令指定存储器件输出从存储器核心访问的数据。 该读取命令包含指定在开始输出数据之前存储器件是否开始输出定时参考信号的信息。 如果信息指定存储器件输出定时参考信号，则存储器控制器接收定时参考信号。 存储器控制器随后基于从存储器件输出的定时参考信号提供的信息对从存储器件输出的数据进行采样。