公开(公告)号：WO2012122381A2

公开(公告)日：2012-09-13

申请号：PCT/US2012/028289

申请日：2012-03-08

Applicant: RAMBUS INC. ,  SHAEFFER, Ian ,  LEI, Luo ,  GOPALAKRISHAN, Liji

Inventor： SHAEFFER, Ian ,  LEI, Luo ,  GOPALAKRISHAN, Liji

IPC: G11C7/22 ,  G11C7/10 ,  G06F1/32

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Abstract translation: 集成电路包括具有控制定时域和数据定时域的物理层接口，以及响应于第一事件而在功率节省模式改变期间实现控制定时域的电路，并且响应于数据定时域 到第二个事件。 控制定时域可以包括耦合到命令和地址路径的接口电路，并且数据定时域可以包括耦合到数据路径的接口电路。

公开(公告)号：WO2011081691A3

公开(公告)日：2011-10-06

申请号：PCT/US2010051318

申请日：2010-10-04

Applicant: RAMBUS INC ,  SHAEFFER IAN ,  VAIDYANATH ARUN ,  MUKHERJEE SANKU

Inventor： SHAEFFER IAN ,  VAIDYANATH ARUN ,  MUKHERJEE SANKU

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F13/1668 ,  G06F1/3275 ,  G06F12/0246 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4072 ,  Y02B60/1228 ,  Y02B60/1235 ,  Y02D10/14 ,  Y02D10/151

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Abstract translation: 一种可扩展存储器系统，其使固定信令带宽能够在专用存储器通道之间可配置地重新分配。 具有逐渐减小的宽度的存储器通道专用于相应的存储器插槽，从而使得能够相对于每个存储器插座的点对点信令，而不会对每个插座的全宽度存储器通道的无负载的插座进行信号损害遍历或昂贵的复制。

公开(公告)号：WO2009111174A1

公开(公告)日：2009-09-11

申请号：PCT/US2009/034491

申请日：2009-02-19

Applicant: RAMBUS INC. ,  HAUKNESS, Brent, S. ,  SHAEFFER, Ian ,  BRONNER, Gary, B.

Inventor： HAUKNESS, Brent, S. ,  SHAEFFER, Ian ,  BRONNER, Gary, B.

IPC: G11C16/14 ,  G11C16/16

CPC classification number: G11C16/16

Abstract: Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device.

Abstract translation: 描述电路的实施例。 该电路包括产生多个分段擦除命令的控制逻辑，以擦除存储在另一个电路内形成的存储器件的存储单元中的信息。 注意，在存储器件内执行多个分段擦除命令中的单个擦除命令可能不足以擦除存储在存储单元中的信息。 此外，第一电路包括从控制逻辑接收多个分段擦除命令并将多个分段擦除命令发送到存储器件的接口。

公开(公告)号：WO2009048707A1

公开(公告)日：2009-04-16

申请号：PCT/US2008/075782

申请日：2008-09-10

Applicant: RAMBUS INC. ,  WOO, Steven C. ,  TSANG, Brian Hing-Kit ,  NG, William N. ,  SHAEFFER, Ian

Inventor： WOO, Steven C. ,  TSANG, Brian Hing-Kit ,  NG, William N. ,  SHAEFFER, Ian

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/08 ,  G06F12/1027 ,  G06F2212/2022 ,  G06F2212/205

Abstract: Embodiments of a circuit are described. This circuit includes an instruction fetch unit to fetch instructions to be executed which are associated with one or more virtual addresses, a translation lookaside buffer (TLB), and an execution unit to execute the instructions. Moreover, the TLB converts virtual addresses into physical addresses. Note that the TLB includes entries for physical addresses that are dedicated to dynamic random access memory (DRAM) and entries for physical addresses that are dedicated to a memory having a storage cell with a retention time that decreases as operations are performed on the storage cell.

Abstract translation: 描述电路的实施例。 该电路包括提取单元以提取与一个或多个虚拟地址相关联的要执行的指令，翻译后备缓冲器（TLB）以及执行指令的执行单元。 此外，TLB将虚拟地址转换为物理地址。 注意，TLB包括专用于动态随机存取存储器（DRAM）的物理地址条目和专用于具有存储单元的存储器的物理地址条目，存储单元具有随着对存储单元执行操作而减少的保留时间。

公开(公告)号：WO2013015893A1

公开(公告)日：2013-01-31

申请号：PCT/US2012/041758

申请日：2012-06-08

Applicant: RAMBUS INC. ,  HARRIS, James, Edward ,  VOGELSANG, Thomas ,  WARE, Frederick, A. ,  SHAEFFER, Ian, P.

Inventor： HARRIS, James, Edward ,  VOGELSANG, Thomas ,  WARE, Frederick, A. ,  SHAEFFER, Ian, P.

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

Abstract translation: 存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。 此外，代替激活响应于行命令的子代码，延迟激活操作被延迟，直到接收到指定要执行的列操作的列命令和被激活的子代。

公开(公告)号：WO2012145117A3

公开(公告)日：2013-01-17

申请号：PCT/US2012029893

申请日：2012-03-21

Applicant: RAMBUS INC ,  GIOVANNINI THOMAS J ,  BEST SCOTT C ,  LUO LEI ,  SHAEFFER IAN

Inventor： GIOVANNINI THOMAS J ,  BEST SCOTT C ,  LUO LEI ,  SHAEFFER IAN

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract translation: 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

公开(公告)号：WO2012145117A2

公开(公告)日：2012-10-26

申请号：PCT/US2012/029893

申请日：2012-03-21

Applicant: RAMBUS INC. ,  GIOVANNINI, Thomas, J. ,  BEST, Scott, C. ,  LUO, Lei ,  SHAEFFER, Ian

Inventor： GIOVANNINI, Thomas, J. ,  BEST, Scott, C. ,  LUO, Lei ,  SHAEFFER, Ian

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract translation: 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

公开(公告)号：WO2012064638A3

公开(公告)日：2012-08-16

申请号：PCT/US2011059550

申请日：2011-11-07

Applicant: RAMBUS INC ,  SHAEFFER IAN ,  WARE FREDERICK A

Inventor： SHAEFFER IAN ,  WARE FREDERICK A

IPC: G06F13/14 ,  G06F12/00 ,  G06F13/38

CPC classification number: G06F12/1458 ,  G06F12/023 ,  G06F13/16 ,  G06F13/1657 ,  G06F13/1684 ,  G06F13/1694 ,  G06F2212/1044 ,  G06F2212/1052

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Abstract translation: 一种多列存储器系统，其中在存储器控制器和一列存储器之间执行校准操作，同时在控制器和其他存储器列之间传输数据。 存储器控制器执行校准操作，该校准操作校准与存储器控制器和第一存储器中的存储器设备之间的第一数据总线有关的数据传输有关的参数。 当控制器执行校准操作时，控制器还通过第二数据总线与第二存储器中的存储器设备传送数据。

公开(公告)号：WO2011106049A1

公开(公告)日：2011-09-01

申请号：PCT/US2010/057902

申请日：2010-11-23

Applicant: RAMBUS INC. ,  SHAEFFER, Ian

Inventor： SHAEFFER, Ian

IPC: G06F13/16 ,  G06F13/38

CPC classification number: G06F13/1694 ,  G06F13/287 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4234

Abstract: A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.

Abstract translation: 存储器控制器通过使用时分复用总线来访问以不同本机速率运行的不同类型的存储器件。 当访问一种类型的存储设备时，以一种速率通过总线传送数据，并且在访问另一种类型的存储设备时以不同的速率传输数据。 此外，存储器控制器可以以不同的速率向不同类型的存储器件提供控制信息（例如，命令和地址信息），并且在一些情况下，将共享总线上的控制信息进行时间复用。

公开(公告)号：WO2011022123A1

公开(公告)日：2011-02-24

申请号：PCT/US2010/040322

申请日：2010-06-29

Applicant: RAMBUS INC. ,  SHAEFFER, Ian

Inventor： SHAEFFER, Ian

IPC: G11C16/34 ,  G11C16/16 ,  G11C7/04

CPC classification number: G11C16/3495 ,  G06F12/1009 ,  G06F2212/1024 ,  H01L27/1052 ,  H01L27/11517 ,  H01L27/11563

Abstract: In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. Tn another system, the memory device is heated to reverse use incurred, degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.

Abstract translation: 在具有存储器件的系统中，在系统操作期间检测到事件。 响应于检测到事件，存储器件被加热以反转存储器件的使用中的劣化。 在另一个系统中，存储设备被加热以逆转使用，与系统的另一个存储设备内的数据访问操作的执行同时降级。 在具有耦合到第一和第二存储器设备的存储器控​​制器的另一系统中，响应于确定在第一存储器设备内需要维护操作，将数据从第一存储器设备撤出到第二存储器设备。