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    BACKSIDE SECURITY SHIELD
    1.
    发明申请
    BACKSIDE SECURITY SHIELD 审中-公开

    公开(公告)号：WO2018106509A1

    公开(公告)日：2018-06-14

    申请号：PCT/US2017063949

    申请日：2017-11-30

    Applicant: CRYPTOGRAPHY RES INC ,  BEST SCOTT C

    Inventor： BEST SCOTT C

    IPC: H04L9/12 ,  G06F21/73 ,  G06K19/07

    Abstract: A physically unclonable function circuit (PUF) is used to generate a fingerprint value based on the uniqueness of the physical characteristics (e.g., resistance, capacitance, connectivity, etc.) of a tamper prevention (i.e., shielding) structure that includes through-silicon vias and metallization on the backside of the integrated circuit. The physical characteristics depend on random physical factors introduced during manufacturing. This causes the chip-to-chip variations in these physical characteristics to be unpredictable and uncontrollable which makes more difficult to duplicate, clone, or modify the structure without changing the fingerprint value. By including the through-silicon vias and metallization on the backside of the integrated circuit as part of the PUF, the backside of the chip can be protected from modifications that can be used to help learn the secure cryptographic keys and/or circumvent the secure cryptographic (or other) circuitry.

    PULSED SIGNALING MULTIPLEXER
    2.
    发明申请
    PULSED SIGNALING MULTIPLEXER 审中-公开
    脉冲信号多路复用器

    公开(公告)号：WO2007064785A2

    公开(公告)日：2007-06-07

    申请号：PCT/US2006/045830

    申请日：2006-11-30

    Applicant: RAMBUS INC. ,  BEST, Scott, C.

    Inventor： BEST, Scott, C.

    IPC: H03M9/00

    CPC classification number: H04J3/02 ,  H04J3/047 ,  H04L25/028 ,  H04L25/493

    Abstract: In one embodiment, a pulsed signaling multiplexer is described that comprises a first AC-coupled transmitter and a second AC-coupled transmitter. The first AC-coupled transmitter includes a first driver having a first input to receive first data and a first output. A first AC-coupling element couples the first output to a common output node. The second AC-coupled transmitter includes a second driver having a second input to receive second data, and a second output. A second AC-coupling element couples the second output to the same first common output node.

    Abstract translation: 在一个实施例中，描述了包括第一AC耦合发射机和第二AC耦合发射机的脉冲信令多路复用器。 第一AC耦合发射机包括具有用于接收第一数据和第一输出的第一输入的第一驱动器。 第一AC耦合元件将第一输出耦合到公共输出节点。 第二AC耦合发射机包括具有用于接收第二数据的第二输入的第二驱动器和第二输出。 第二AC耦合元件将第二输出耦合到相同的第一公共输出节点。

    SELF-TIMED INTERFACE FOR STROBE-BASED SYSTEMS
    3.
    发明申请
    SELF-TIMED INTERFACE FOR STROBE-BASED SYSTEMS 审中-公开
    用于基于STROBE的系统的自定义接口

    公开(公告)号：WO2006099147A1

    公开(公告)日：2006-09-21

    申请号：PCT/US2006/008610

    申请日：2006-03-10

    Applicant: RAMBUS INC. ,  BEST, Scott, C. ,  KIZER, Jade, M.

    Inventor： BEST, Scott, C. ,  KIZER, Jade, M.

    IPC: G06F13/40 ,  G06F13/38 ,  G06F5/06

    CPC classification number: G06F13/4059

    Abstract: Self-timed interfaces and methods are provided for interfacing different timing domains. These self-timed interfaces receive a strobe signal from a component operating under a first clock domain. A first signal path of the self-timed interface couples the strobe signal to a receiver that samples data of data line under control of the strobe signal. A second signal path of the self-timed interface couples the strobe signal to an interface circuit through a hysteresis-based element. The interface circuit, under control of an output of the hysteresis-based element along with a clock signal that originates under a second clock domain, generates an interface enable signal for use in controlling data transfers between the different clock domains.

    Abstract translation: 提供自定义接口和方法来连接不同的定时域。 这些自定时接口从在第一时钟域下运行的组件接收选通信号。 自定时接口的第一信号路径将选通信号耦合到在选通信号的控制下采样数据线的数据的接收机。 自定时接口的第二信号路径通过基于滞后的元件将选通信号耦合到接口电路。 接口电路在基于滞后的元件的输出的控制下以及起始于第二时钟域的时钟信号产生用于控制不同时钟域之间的数据传输的接口使能信号。

    COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE GENERATED REFERENCE SIGNALS
    5.
    发明申请
    COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE GENERATED REFERENCE SIGNALS 审中-公开
    使用存储器件生成的参考信号协调存储器操作

    公开(公告)号：WO2011106055A1

    公开(公告)日：2011-09-01

    申请号：PCT/US2010/058542

    申请日：2010-12-01

    Applicant: RAMBUS INC. ,  BEST, Scott C. ,  SHAEFFER, Ian

    Inventor： BEST, Scott C. ,  SHAEFFER, Ian

    IPC: G06F13/16 ,  G06F13/38

    CPC classification number: G06F13/1689 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  Y02D10/14

    Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

    Abstract translation: 存储器系统包括耦合到多个存储器件的存储器控​​制器。 每个存储器件包括产生内部参考信号的振荡器，该内部参考信号以存储器件内的物理器件结构的函数的频率振荡。 因此，内部参考信号的频率是器件特定的。 每个存储器件从其内部参考信号产生共享参考信号，并将共享参考信号传送到公共存储器控制器。 存储器控制器使用共享参考信号从每个存储器件恢复器件特定的频率信息，然后以与相应的内部参考信号兼容的频率与每个存储器件通信。

    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS
    7.
    发明申请
    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS 审中-公开
    用于通信信道的移动跟踪反馈

    公开(公告)号：WO2005089407A3

    公开(公告)日：2005-12-22

    申请号：PCT/US2005008830

    申请日：2005-03-16

    Applicant: RAMBUS INC ,  BEST SCOTT C ,  ABHYANKAR ABHIJIT M ,  CHANG KUN-YUNG ,  LAMBRECHT FRANK

    Inventor： BEST SCOTT C ,  ABHYANKAR ABHIJIT M ,  CHANG KUN-YUNG ,  LAMBRECHT FRANK

    IPC: G06F1/04 ,  H04L7/00 ,  H04L7/10 ,  H04L25/14

    CPC classification number: G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

    Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

    Abstract translation: 通信信道包括具有耦合到正常信号源的发射器​​的第一组件和具有耦合到正常信号目的地的接收器的第二组件。 通信链路耦合第一和第二组件。 校准逻辑规定为通信信道的参数设置操作值，例如通过在链路初始化时执行穷举校准序列。 包括监测功能的跟踪电路通过监测具有与通信信道中的漂移相关的特性的反馈信号来跟踪参数中的漂移，并且更新或指示需要更新参数的操作值 响应监测功能。

    MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES
    8.
    发明申请
    MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES 审中-公开
    存储器组件和控制器，用于校准多个同步时序参考

    公开(公告)号：WO2012145117A3

    公开(公告)日：2013-01-17

    申请号：PCT/US2012029893

    申请日：2012-03-21

    Applicant: RAMBUS INC ,  GIOVANNINI THOMAS J ,  BEST SCOTT C ,  LUO LEI ,  SHAEFFER IAN

    Inventor： GIOVANNINI THOMAS J ,  BEST SCOTT C ,  LUO LEI ,  SHAEFFER IAN

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

    Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

    Abstract translation: 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

    MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES
    9.
    发明申请
    MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES 审中-公开
    存储器组件和控制器，用于校准多个同步时序参考

    公开(公告)号：WO2012145117A2

    公开(公告)日：2012-10-26

    申请号：PCT/US2012/029893

    申请日：2012-03-21

    Applicant: RAMBUS INC. ,  GIOVANNINI, Thomas, J. ,  BEST, Scott, C. ,  LUO, Lei ,  SHAEFFER, Ian

    Inventor： GIOVANNINI, Thomas, J. ,  BEST, Scott, C. ,  LUO, Lei ,  SHAEFFER, Ian

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

    Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

    Abstract translation: 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

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