Abstract:
An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with a first layer and a second mark portion associated with a second layer, wherein the first and second mark portions comprise geometrically similar periodic arrays of mark structures laid down such that the mark portions have patterns exhibiting rotational symmetry with the axes coincident when the mark is in correct alignment whereby the first mark portion overlays the second mark portion when in correct alignment to create an overlap region, but wherein the periodic array of the first mark portion is systematically shifted relative to the periodic array of the second mark portion to generate a Moiré fringe effect in at least a part of the overlap region. A method of marking and a method of determining overlay error are also described.
Abstract:
An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with and in particular developed on a first layer and a second mark portion associated with and in particular developed on a second layer, wherein the first and second mark portions together constitute, when the mark is properly aligned, at least one pair of test zones, each test zone comprising a first mark section formed as part of the first mark portion and a second mark section formed as part of the second mark portion each comprising a plurality of elongate rectangular mark structures in parallel array adjacently disposed to form the said test zone such that the mark structures in each test zone are in alignment in a first direction within the test zone but are substantially at 90° with respect to the mark structures of at least one other test zone in alignment in a second direction, and wherein the test zones making up the or each pair are laterally displaced relative to each other along one of the said directions. A method of marking and a method of determining overlay error are also described.
Abstract:
A method of automatically focusing a microscope having a light source, an objective lens or lens system, a means to direct incident light through the objective lens or lens system to be reflected by the object, an aperture to limit the spatial extent of the incident light and serve as an illumination pupil, a means to direct at least some of the reflected light to an imaging system, and an imaging system to image the reflected light so directed is described. In accordance with the invention a beam of light is directed from a light source through an objective of the microscope system to an object whereby light is reflected from the surface thereof; reflected light is collected and directed to an imaging system, wherein the incident beam of light is limited in spatial extent by imaging an aperture to form an illumination pupil, the centroid of illumination of the illumination pupil is aligned with the incident optical axis of the instrument, and reflected light is projected to the imaging system comprising at least one pair of images from eccentric sections of an imaging pupil displaced from the optical axis in opposite directions, and wherein the separation of the images thereby produced is determined to provide an indication of the object distance. A focusing system implementing the method and a microscope fitted with such a system are also described.
Abstract:
The invention relates to a method and means for automatic focusing and has particular use in semiconductor metrology. The invention concerns the use of two beam sources and a single detector. One of said beam sources is projected forwardly of an image plane of an object to be viewed and the second of said beam sources is projected rearwardly of an image plane of an object to be viewed. The reflections from each of said beams are then passed through a vignetting aperture and onto a single focus detector. Using this arrangement it is possible to efficiently and accurately determine the point of focus.
Abstract:
The invention relates to a novel housing for an optical instrument such as a microscope. The housing is provided with a number of channel means which are positioned having regard to the optical axis of the instrument and adapted to accommodate a plurality of optical components so as to facilitate the alignment of same.
Abstract:
Scatterometers and methods of using scatterometry to determine several parameters of periodic microstructures, pseudo-periodic structures, and other very small structures having features sizes as small as 100 nm or less. Several specific embodiments of the present invention are particularly useful in the semiconductor industry to determine the width, depth, line edge roughness, wall angle, film thickness, and many other parameters of the features formed in microprocessors, memory devices, and other semiconductor devices. The scatterometers and methods of the invention, however, are not limited t semiconductor applications and can be applied equally well in other applications. The scatterometer contains a positioning system and an auto-focus system.
Abstract:
Scatterometers and methods of using scatterometry to determine several parameters of periodic microstructures, pseudo-periodic structures, and other very small structures having features sizes as small as 100 nm or less. Several specific embodiments of the present invention are particularly useful in the semiconductor industry to determine the width, depth, line edge roughness, wall angle, film thickness, and many other parameters of the features formed in microprocessors, memory devices, and other semiconductor devices. The sensitivity of single pixels of the camera on changes in a measured parameter is modelled and only pixels with a high sensitivity are considered for the measurement.
Abstract:
An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with a first layer and a second mark portion associated with a second layer, wherein the first and second mark portions comprise geometrically similar periodic arrays of mark structures laid down such that the mark portions have patterns exhibiting rotational symmetry with the axes coincident when the mark is in correct alignment whereby the first mark portion overlays the second mark portion when in correct alignment to create an overlap region, but wherein the periodic array of the first mark portion is systematically shifted relative to the periodic array of the second mark portion to generate a Moiré fringe effect in at least a part of the overlap region. A method of marking and a method of determining overlay error are also described.
Abstract:
Scatterometers and methods of using scatterometry to determine several parameters of periodic microstructures, pseudo-periodic structures, and other very small structures having features sizes as small as 100 nm or less. Several specific embodiments of the present invention are particularly useful in the semiconductor industry to determine the width, depth, line edge roughness, wall angle, film thickness, and many other parameters of the features formed in microprocessors, memory devices, and other semiconductor devices. The scatterometers and methods of the invention, however, are not limited t semiconductor applications and can be applied equally well in other applications. The scatterometer contains a positioning system and an auto-focus system.
Abstract:
Scatterometers and methods of using scatterometry to determine several parameters of periodic microstructures, pseudo-periodic structures, and other very small structures having features sizes as small as 100 nm or less. Several specific embodiments of the present invention are particularly useful in the semiconductor industry to determine the width, depth, line edge roughness, wall angle, film thickness, and many other parameters of the features formed in microprocessors, memory devices, and other semiconductor devices. The scatterometers and methods of the invention, however, are not limited to semiconductor applications and can be applied equally well in other applications.