公开(公告)号：WO2013048693A1

公开(公告)日：2013-04-04

申请号：PCT/US2012/054112

申请日：2012-09-07

Applicant: RAYTHEON COMPANY ,  LAROCHE, Jeffrey, R. ,  KAZIOR, Thomas, E. ,  HOKE, William, E.

Inventor： LAROCHE, Jeffrey, R. ,  KAZIOR, Thomas, E. ,  HOKE, William, E.

IPC: H01L21/8258 ,  H01L27/12

CPC classification number: H01L21/8258 ,  H01L27/1207

Abstract: A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.

Abstract translation: 具有形成在该结构的化合物半导体中的化合物半导体（CS）器件的半导体结构和形成在该结构的元素半导体层中的元素半导体器件。 该结构包括具有元素半导体器件的层设置在掩埋氧化物（BOX）层上。 选择性蚀刻层设置在BOX层和化合物半导体器件的层之间。 选择性蚀刻层能够选择性地蚀刻BOX层，从而最大化在蚀刻窗口中生长的化合物半导体器件的垂直和侧向窗蚀刻工艺控制。 选择性蚀刻层具有比BOX层的蚀刻速率更低的蚀刻速率。

公开(公告)号：WO2006124387A3

公开(公告)日：2010-09-02

申请号：PCT/US2006017823

申请日：2006-05-09

Applicant: RAYTHEON CO ,  HOKE WILLIAM E ,  MOSCA JOHN J

Inventor： HOKE WILLIAM E ,  MOSCA JOHN J

IPC: H01L29/778 ,  H01L21/335 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/7785

Abstract: A semiconductor structure, comprising: a substrate; a first aluminum nitride (AlN) layer having an aluminum/reactive nitride (Al/N) flux ratio less than 1 disposed on the substrate; and a second AlN layer having an Al/reactive N flux ratio greater than 1 disposed on the first AlN layer. The substrate is a compound of silicon wherein the first AlN layer is substantially free of silicon.

Abstract translation: 一种半导体结构，包括：基板; 具有设置在基板上的铝/反应性氮化物（Al / N）通量比小于1的第一氮化铝（AlN）层; 以及具有设置在第一AlN层上的大于1的Al /反应性N通量比的第二AlN层。 衬底是硅的化合物，其中第一AlN层基本上不含硅。

公开(公告)号：WO2008057193A1

公开(公告)日：2008-05-15

申请号：PCT/US2007/022325

申请日：2007-10-19

Applicant: RAYTHEON COMPANY ,  LAROCHE, Jeffrey, R. ,  HOKE, William, E. ,  BERNSTEIN, Steven, D. ,  KORENSTEIN, Ralph

Inventor： LAROCHE, Jeffrey, R. ,  HOKE, William, E. ,  BERNSTEIN, Steven, D. ,  KORENSTEIN, Ralph

IPC: H01L29/267 ,  H01L29/778

CPC classification number: C04B35/583 ,  C04B35/581 ,  H01L29/045 ,  H01L29/1602 ,  H01L29/242 ,  H01L29/267 ,  H01L29/365 ,  H01L29/7782 ,  H01L29/7787

Abstract: A heterostructire having a heteroj unction comprising: a diamond layer; and a boron aluminum nitride (B(X)A1(|.X)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.

Abstract translation: 具有异质结构的异质结构包括：金刚石层; 和与金刚石层的表面接触设置的氮化铝硼（B（X）A1（| .X）N）层，其中x在0和1之间。

公开(公告)号：WO2005006445A1

公开(公告)日：2005-01-20

申请号：PCT/US2004/016335

申请日：2004-05-25

Applicant: RAYTHEON COMPANY ,  MARSH, Philbert, F. ,  WHELAN, Colin, S. ,  HOKE, William, E.

Inventor： MARSH, Philbert, F. ,  WHELAN, Colin, S. ,  HOKE, William, E.

IPC: H01L29/778

CPC classification number: H01L29/7784

Abstract: A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; an indium aluminum gallium arsenide (InAlGaAs) lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an In y Ga 1-y As lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an In x Ga 1-x As upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the In x Ga 1-x As upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer and the lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer.

Abstract translation: 具有砷化镓（GaAs）半导体衬底的晶体管结构; 铟铝砷化镓（InAlGaAs）晶格匹配层; 设置在晶格匹配层上的铟铝砷化物（InAlAs）阻挡层; Iny Ga1-y作为设置在阻挡层上的下通道层，其中y是下通道层中In含量的摩尔分数; Inx Ga1-x作为上通道层，其设置在下通道层上，其中x是上通道层中In含量的摩尔分数，其中x不同于y; 和Inx Ga1-x As上通道层上的InAlAs肖特基层。 下沟道层的带隙大于上沟道层和下沟道层的带隙具有低于上沟道层的体电子迁移率的体电子迁移率。

公开(公告)号：WO2011094190A1

公开(公告)日：2011-08-04

申请号：PCT/US2011/022358

申请日：2011-01-25

Applicant: RAYTHEON COMPANY ,  HOKE, William, E. ,  LAROCHE, Jeffrey, R.

Inventor： HOKE, William, E. ,  LAROCHE, Jeffrey, R.

IPC: H01L21/8258 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L27/1207 ,  H01L21/76251 ,  H01L21/8258 ,  H01L29/045 ,  H01L29/267

Abstract: A semiconductor structure having: a silicon substrate (12) having a crystallographic orientation; an insulating layer (18/22) disposed over the silicon substrate (12); a silicon layer (20) having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device (34) having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In other embodiments, the device is a GaN device or the crystallographic orientation of the substrate is and wherein the crystallographic orientation of the silicon layer is . In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the silicon layer.

Abstract translation: 一种半导体结构，具有：具有晶体取向的硅衬底（12） 设置在所述硅衬底（12）上的绝缘层（18/22）; 具有与设置在所述绝缘层上的所述衬底的晶体取向不同的晶体取向的硅层（20）; 和具有与设置在硅衬底上的衬底相同的晶体取向的列III-V晶体管器件（34）。 在一个实施例中，列III-V晶体管器件与衬底接触。 在其他实施例中，器件是GaN器件，或者衬底的晶体取向为“1”，并且其中硅层的晶体取向为100。 在一个实施例中，CMOS晶体管设置在硅层中。 在一个实施例中，列III-V晶体管器件是III-N族器件。 在一个实施例中，III-As，III-P或III-Sb元件设置在<100>硅层的顶部。

公开(公告)号：WO2011028461A1

公开(公告)日：2011-03-10

申请号：PCT/US2010/046283

申请日：2010-08-23

Applicant: RAYTHEON COMPANY ,  CHUMBES, Eduardo, M. ,  HOKE, William, E. ,  IP, Kelly, P. ,  SHAW, Dale, M. ,  BRIERLEY, Steven, K.

Inventor： CHUMBES, Eduardo, M. ,  HOKE, William, E. ,  IP, Kelly, P. ,  SHAW, Dale, M. ,  BRIERLEY, Steven, K.

IPC: H01L21/8252 ,  H01L27/06 ,  H01L21/311

CPC classification number: H01L21/8252 ,  H01L21/31111 ,  H01L27/0605

Abstract: A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer.

Abstract translation: 一种在半导体表面上形成结构的方法。 该方法包括：使用第一沉积工艺将所述材料形成为所述结构的下层，以向所述下层提供预定蚀刻剂的第一蚀刻速率; 使用第二沉积工艺在所述下部材料上形成所述结构的上层，以向所述上层提供比所述第一蚀刻速率高的所述预定蚀刻剂的第二蚀刻速率; 并将预定的蚀刻剂施加到上层，以选择性地移除上部，同时离开下层。

公开(公告)号：WO2007030316A2

公开(公告)日：2007-03-15

申请号：PCT/US2006032748

申请日：2006-08-23

Applicant: RAYTHEON CO ,  HOKE WILLIAM E

Inventor： HOKE WILLIAM E

IPC: H01L29/20 ,  H01L29/778

CPC classification number: H01L29/7785

Abstract: A semiconductor structure having a III-V substrate; a first III-V donor layer having a relatively wide bandgap disposed over the substrate; a III-V channel layer having a relatively narrow bandgap disposed on the donor layer; a second III-V donor layer disposed on the channel layer having a relatively wide bandgap. The first III-V donor provides both tensile strain to compensate compressive strain in the channel layer and carriers to the channel layer.

Abstract translation: 具有III-V族衬底的半导体结构; 具有相对宽带隙的第一III-V施主层设置在衬底上; 设置在施主层上的具有相对窄带隙的III-V沟道层; 设置在具有较宽带隙的沟道层上的第二III-V施主层。 第一个III-V施主提供拉伸应变以补偿沟道层和载流子中沟道层的压缩应变。

公开(公告)号：WO2006124387A2

公开(公告)日：2006-11-23

申请号：PCT/US2006/017823

申请日：2006-05-09

Applicant: RAYTHEON COMPANY ,  HOKE, William, E. ,  MOSCA, John, J.

Inventor： HOKE, William, E. ,  MOSCA, John, J.

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/7785

Abstract: A semiconductor structure, comprising: a substrate; a first aluminum nitride (AlN) layer having an aluminum/reactive nitride (Al/N) flux ratio less than 1 disposed on the substrate; and a second AlN layer having an Al/reactive N flux ratio greater than 1 disposed on the first AlN layer. The substrate is a compound of silicon wherein the first AlN layer is substantially free of silicon.

Abstract translation: 一种半导体结构，包括：基板; 具有设置在基板上的铝/反应性氮化物（Al / N）通量比小于1的第一氮化铝（AlN）层; 以及具有设置在第一AlN层上的大于1的Al /反应性N通量比的第二AlN层。 衬底是硅的化合物，其中第一AlN层基本上不含硅。

公开(公告)号：WO2012145089A1

公开(公告)日：2012-10-26

申请号：PCT/US2012/028389

申请日：2012-03-09

Applicant: RAYTHEON COMPANY ,  HOKE, William, E.

Inventor： HOKE, William, E.

IPC: H01L21/02

CPC classification number: H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549

Abstract: A semiconductor structure having: a column IV material or column IV-IV material; a nucleation layer of AlN layer or a column III nitride having more than 60% aluminum content on a surface of the column IV material or column IV-IV material and a layer of column III-V material over the nucleation layer, where the nucleation layer and the layer of column III-V material over the nucleation layer have different crystallographic structures. In one embodiment, the column III-V nucleation layer is a nitride and the column III- V material of the over the nucleation layer is a non-nitride such as, for example, an arsenide (e.g., GaAs), a phosphide (e.g., InP), or an antimonide (e.g. InSb), or alloys thereof.

Abstract translation: 具有柱IV材料或第IV-IV族材料的半导体结构; AlN层的成核层或在IV族材料或第IV-IV族材料的表面上具有超过60％的铝含量的III族氮化物，以及成核层上的III-V族材料层，其中成核层 并且成核层上的III-V族材料层具有不同的晶体结构。 在一个实施方案中，III-V族成核层是氮化物，并且成核层之上的III-V族材料是非氮化物，例如砷化物（例如GaAs），磷化物（例如， ，InP）或锑化物（例如InSb）或其合金。

公开(公告)号：WO2011005444A1

公开(公告)日：2011-01-13

申请号：PCT/US2010/038992

申请日：2010-06-17

Applicant: RAYTHEON COMPANY ,  RESLER, Daniel, P. ,  HOKE, William, E.

Inventor： RESLER, Daniel, P. ,  HOKE, William, E.

IPC: G02F1/1343 ,  H01L29/778 ,  H01L21/335

CPC classification number: G02F1/13439 ,  H01L29/2003 ,  H01L29/7787

Abstract: Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium flouride buffer layer),and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer),and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.

Abstract translation: 这里描述的是具有氮化镓HEMT电极的液晶（LC）器件。 氮化镓HEMT电极可以在各种基底上生长，包括但不限于蓝宝石，碳化硅，硅，熔融二氧化硅（使用硅酸钙缓冲层）和尖晶石。 还描述了从在大面积硅衬底上生长的GaN HEMT提供的结构，并将其转移到具有用于OPA器件的适当性质的另一衬底。 这种衬底包括但不限于蓝宝石，碳化硅，硅，熔融二氧化硅（使用氟化钙缓冲层）和尖晶石。 GaN HEMT结构包括用于改善结构的迁移率的AlN夹层。