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    STRUCTURE HAVING MONOLITHIC HETEROGENEOUS INTEGRATION OF COMPOUND SEMICONDUCTORS WITH ELEMENTAL SEMICONDUCTOR
    2.
    发明申请
    STRUCTURE HAVING MONOLITHIC HETEROGENEOUS INTEGRATION OF COMPOUND SEMICONDUCTORS WITH ELEMENTAL SEMICONDUCTOR 审中-公开
    具有复合半导体与单片半导体的单晶异质整体结构

    公开(公告)号：WO2013048693A1

    公开(公告)日：2013-04-04

    申请号：PCT/US2012/054112

    申请日：2012-09-07

    Applicant: RAYTHEON COMPANY ,  LAROCHE, Jeffrey, R. ,  KAZIOR, Thomas, E. ,  HOKE, William, E.

    Inventor： LAROCHE, Jeffrey, R. ,  KAZIOR, Thomas, E. ,  HOKE, William, E.

    IPC: H01L21/8258 ,  H01L27/12

    CPC classification number: H01L21/8258 ,  H01L27/1207

    Abstract: A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.

    Abstract translation: 具有形成在该结构的化合物半导体中的化合物半导体（CS）器件的半导体结构和形成在该结构的元素半导体层中的元素半导体器件。 该结构包括具有元素半导体器件的层设置在掩埋氧化物（BOX）层上。 选择性蚀刻层设置在BOX层和化合物半导体器件的层之间。 选择性蚀刻层能够选择性地蚀刻BOX层，从而最大化在蚀刻窗口中生长的化合物半导体器件的垂直和侧向窗蚀刻工艺控制。 选择性蚀刻层具有比BOX层的蚀刻速率更低的蚀刻速率。

    GOLD-FREE OHMIC CONTACTS
    5.
    发明申请
    GOLD-FREE OHMIC CONTACTS 审中-公开
    无黄金联系人

    公开(公告)号：WO2012166385A1

    公开(公告)日：2012-12-06

    申请号：PCT/US2012/038497

    申请日：2012-05-18

    Applicant: RAYTHEON COMPANY ,  CHELAKARA, Ram, V. ,  KAZIOR, Thomas, E. ,  LAROCHE, Jeffrey, R.

    Inventor： CHELAKARA, Ram, V. ,  KAZIOR, Thomas, E. ,  LAROCHE, Jeffrey, R.

    IPC: H01L29/45 ,  H01L29/20 ,  H01L29/778

    CPC classification number: H01L29/452 ,  H01L29/2003 ,  H01L29/7787

    Abstract: A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material.

    Abstract translation: 提供一种半导体结构，其具有：半导体; 与半导体欧姆接触的无金导电结构; 以及一层由硅层隔开的导电层。 该结构包括：与半导体接触设置的难熔金属层; 并且其中由所述硅层分离的所述一对导电层中的一个是难熔金属层。 第二层硅层被设置在一对导电层中的第二层上，并且在第二层硅上包括第三导电层。 在一个实施例中，半导体包括III-V材料。

    SEMICONDUCTOR STRUCTURE HAVING SILICON CMOS TRANSISTORS WITH COLUMN III-V TRANSISTORS ON A COMMON SUBSTRATE
    6.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING SILICON CMOS TRANSISTORS WITH COLUMN III-V TRANSISTORS ON A COMMON SUBSTRATE 审中-公开
    具有通用基板上的III-V晶体管的硅CMOS晶体管的半导体结构

    公开(公告)号：WO2011094190A1

    公开(公告)日：2011-08-04

    申请号：PCT/US2011/022358

    申请日：2011-01-25

    Applicant: RAYTHEON COMPANY ,  HOKE, William, E. ,  LAROCHE, Jeffrey, R.

    Inventor： HOKE, William, E. ,  LAROCHE, Jeffrey, R.

    IPC: H01L21/8258 ,  H01L27/12 ,  H01L29/04

    CPC classification number: H01L27/1207 ,  H01L21/76251 ,  H01L21/8258 ,  H01L29/045 ,  H01L29/267

    Abstract: A semiconductor structure having: a silicon substrate (12) having a crystallographic orientation; an insulating layer (18/22) disposed over the silicon substrate (12); a silicon layer (20) having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device (34) having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In other embodiments, the device is a GaN device or the crystallographic orientation of the substrate is and wherein the crystallographic orientation of the silicon layer is . In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the silicon layer.

    Abstract translation: 一种半导体结构，具有：具有晶体取向的硅衬底（12） 设置在所述硅衬底（12）上的绝缘层（18/22）; 具有与设置在所述绝缘层上的所述衬底的晶体取向不同的晶体取向的硅层（20）; 和具有与设置在硅衬底上的衬底相同的晶体取向的列III-V晶体管器件（34）。 在一个实施例中，列III-V晶体管器件与衬底接触。 在其他实施例中，器件是GaN器件，或者衬底的晶体取向为“1”，并且其中硅层的晶体取向为100。 在一个实施例中，CMOS晶体管设置在硅层中。 在一个实施例中，列III-V晶体管器件是III-N族器件。 在一个实施例中，III-As，III-P或III-Sb元件设置在<100>硅层的顶部。

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