公开(公告)号：WO2009051716A3

公开(公告)日：2009-04-23

申请号：PCT/US2008/011753

申请日：2008-10-15

Applicant: MICRON TECHNOLOGY, INC. ,  KEETH, Brent

Inventor： KEETH, Brent

IPC: H01L21/66

Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

公开(公告)号：WO2007005218B1

公开(公告)日：2007-04-26

申请号：PCT/US2006023219

申请日：2006-06-14

Applicant: MICRON TECHNOLOGY INC ,  MARTIN CHRIS G ,  MANNING TROY A ,  KEETH BRENT

Inventor： MARTIN CHRIS G ,  MANNING TROY A ,  KEETH BRENT

IPC: G11C29/00

CPC classification number: G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Abstract translation: 一种用于修复半导体存储器件的装置和方法包括第一存储器单元阵列，第一冗余单元阵列和修复电路，该修复电路被配置为非易失性地将指定至少一个故障存储器单元的第一地址存储在第一存储器单元阵列中。 第一易失性高速缓存存储对应于指定至少一个有缺陷的存储单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个故障存储单元的第一地址分配给第一易失性缓存。 当第一存储器访问对应于第一高速缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储器单元替换为第一存储器单元阵列中的至少一个有缺陷存储器单元。

公开(公告)号：WO2006026526A2

公开(公告)日：2006-03-09

申请号：PCT/US2005/030593

申请日：2005-08-26

Applicant: MICRON TECHNOLOGY, INC. ,  LIN, Feng ,  KEETH, Brent ,  JOHNSON, Brian ,  LEE, Seong-hoon

Inventor： LIN, Feng ,  KEETH, Brent ,  JOHNSON, Brian ,  LEE, Seong-hoon

IPC: G11C7/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

Abstract translation: 存储器系统将命令，地址或写入数据信号从存储器控制器耦合到存储器件，并将数据信号从存储器件读取到存储器控制器。 每个存储器控制器和存储器件中的相应选通发生器电路都产生同相选通信号和正交选通信号。 存储在存储器控制器中的相应输出锁存器中的命令，地址或写数据信号由来自内部选通发生器电路的同相信号计时。 这些命令，地址或写入数据信号通过从存储器控制器耦合到存储器件的正交选通信号而被锁存在存储器件中的输入锁存器中。 以基本上相同的方式，使用由内部选通发生器电路产生的同相和正交选通信号，将读数据信号从存储器件耦合到存储器控制器。

公开(公告)号：WO2004001846A3

公开(公告)日：2004-10-28

申请号：PCT/US0321029

申请日：2003-06-18

Applicant: MICRON TECHNOLOGY INC ,  BATRA SHUBNEESH ,  CHAINE MICHAEL D ,  KEETH BRENT ,  AKRAM SALMAN ,  MANNING TROY A ,  JOHNSON BRIAN ,  MARTIN CHRIS G ,  MERRITT TODD A ,  SMITH ERIC J

Inventor： BATRA SHUBNEESH ,  CHAINE MICHAEL D ,  KEETH BRENT ,  AKRAM SALMAN ,  MANNING TROY A ,  JOHNSON BRIAN ,  MARTIN CHRIS G ,  MERRITT TODD A ,  SMITH ERIC J

IPC: H01L23/485 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L24/05 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01061 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105

Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

Abstract translation: 描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。 该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘 （26b）在所述一个或多个下层金属层中的每一个上。 在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。 寄生电容因此大大降低，信号传播速度提高。

公开(公告)号：WO2011126893A2

公开(公告)日：2011-10-13

申请号：PCT/US2011/030544

申请日：2011-03-30

Applicant: MICRON TECHNOLOGY, INC. ,  KEETH, Brent ,  MORZANO, Christopher K.

Inventor： KEETH, Brent ,  MORZANO, Christopher K.

CPC classification number: H01L25/0652 ,  G06F13/385 ,  G11C5/02 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

Abstract translation: 各种实施例包括在接口管芯上形成骰子堆叠的装置，堆叠装置和方法。 在一种这样的装置中，骰子堆叠包括至少第一模具和第二模具，以及将第一模具和第二模具耦合到公共控制模具的导电路径。 在一些实施例中，导电路径可以布置成与堆叠的交替管芯上的电路连接。 在其他实施例中，多个骰子堆可以被布置在单个接口管芯上，并且骰子的一些或全部可以具有交错导电路径。

公开(公告)号：WO2006118788A3

公开(公告)日：2009-05-07

申请号：PCT/US2006014650

申请日：2006-04-17

Applicant: MICRON TECHNOLOGY INC ,  JANZEN JEFFREY W ,  KEETH BRENT ,  WRIGHT JEFFREY P ,  CULLUM JAMES S

Inventor： JANZEN JEFFREY W ,  KEETH BRENT ,  WRIGHT JEFFREY P ,  CULLUM JAMES S

IPC: G06F12/02

CPC classification number: G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

Abstract translation: 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

公开(公告)号：WO2007005218A1

公开(公告)日：2007-01-11

申请号：PCT/US2006/023219

申请日：2006-06-14

Applicant: MICRON TECHNOLOGY, INC. ,  MARTIN, Chris, G. ,  MANNING, Troy, A. ,  KEETH, Brent

Inventor： MARTIN, Chris, G. ,  MANNING, Troy, A. ,  KEETH, Brent

IPC: G11C29/00

CPC classification number: G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Abstract translation: 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一高速缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

公开(公告)号：WO2011126893A3

公开(公告)日：2012-02-02

申请号：PCT/US2011030544

申请日：2011-03-30

Applicant: MICRON TECHNOLOGY INC ,  KEETH BRENT ,  MORZANO CHRISTOPHER K

Inventor： KEETH BRENT ,  MORZANO CHRISTOPHER K

IPC: H01L23/52 ,  H01L23/12

CPC classification number: H01L25/0652 ,  G06F13/385 ,  G11C5/02 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

Abstract translation: 各种实施例包括在接口管芯上形成骰子堆叠的装置，堆叠装置和方法。 在一种这样的装置中，骰子堆叠包括至少第一模具和第二模具，以及将第一模具和第二模具耦合到公共控制模具的导电路径。 在一些实施例中，导电路径可以布置成与堆叠的交替管芯上的电路连接。 在其他实施例中，多个骰子堆可以被布置在单个接口管芯上，并且骰子的一些或全部可以具有交错导电路径。

公开(公告)号：WO2010030799A1

公开(公告)日：2010-03-18

申请号：PCT/US2009/056538

申请日：2009-09-10

Applicant: MICRON TECHNOLOGY, INC. ,  KEETH, Brent

Inventor： KEETH, Brent

IPC: H01L23/12 ,  H01L23/48

CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/20 ,  G11C2207/2227 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die.

Abstract translation: 一些实施例包括具有布置在堆叠中的骰子的装置和方法。 骰子至少包括第一管芯和第二管芯，以及连接到管芯的连接。 连接可以被配置为在将第一标识分配给第一管芯期间将控制信息传送到第一管芯，并且在将第二标识分配给第二管芯期间将控制信息从第一管芯传送到第二管芯。

公开(公告)号：WO2009051716A2

公开(公告)日：2009-04-23

申请号：PCT/US2008011753

申请日：2008-10-15

Applicant: MICRON TECHNOLOGY INC ,  KEETH BRENT

Inventor： KEETH BRENT

IPC: H01L21/66

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C29/02 ,  G11C29/022 ,  G11C29/70 ,  G11C2029/3202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/1531 ,  H01L2924/00

Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects in the connections.

Abstract translation: 一些实施例包括包括布置在堆叠中的半导体裸片的装置，系统和方法，被配置为提供骰子之间的通信的多个连接，穿过至少一个骰子的连接的至少一部分，以及被配置为 检查连接中的缺陷并修复连接中的缺陷。