公开(公告)号：WO2007137049A3

公开(公告)日：2008-01-31

申请号：PCT/US2007069002

申请日：2007-05-16

Applicant: IBM ,  BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

Inventor： BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon (110A and 110B) from two silicon-on- insulator wafers (110A and 100B), respectively, having devices (130A and 130B), respectively, fabricated therein and bonding them back to back utilizing the buried oxide layers (115). Contacts (210) are then formed in the upper wafer (I00B) to devices (130A) in the lower wafer (100A) and wiring levels (170) are formed on the upper wafer (100B). The lower wafer (100A) may include wiring levels (170). The lower wafer (100A) may include landing pads (230) for the contacts. Contacts to the silicon layer (120) of the lower wafer (100A) may be silicided.

Abstract translation: 一种半导体结构及其制造方法。 该方法包括从分别制造在其中的器件（130A和130B）的两个绝缘体上硅晶片（110A和100​​B）去除后侧硅（110A和110B），并使用掩埋氧化物 层（115）。 接触件（210）然后在上晶片（I00B）中形成在下晶片（100A）中的器件（130A），并且布线层（170）形成在上晶片（100B）上。 下晶片（100A）可以包括布线​​层（170）。 下晶片（100A）可以包括用于触点的着陆焊盘（230）。 与下晶片（100A）的硅层（120）的接触可以被硅化。

公开(公告)号：WO2008055887A1

公开(公告)日：2008-05-15

申请号：PCT/EP2007/061904

申请日：2007-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  LUCE, Stephen, Ellinwood ,  MCDEVITT, Thomas, Leddy ,  STAMPER, Anthony

Inventor： LUCE, Stephen, Ellinwood ,  MCDEVITT, Thomas, Leddy ,  STAMPER, Anthony

IPC: H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76801 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different fro m the first electrically conduct ive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.

Abstract translation: 一种结构及其形成方法。 该结构包括（a）层间电介质层（ILD）层; （b）位于ILD层中的第一导电线和第二导电线; （c）位于ILD层中的扩散阻挡区域。 扩散阻挡区（i）物理隔离，（ii）电耦合在一起，和（iii）与第一和第二导电线直接物理接触。 第一和第二导电线各自包括第一导电材料。 扩散阻挡区域包括与第一导电材料不同的第二导电材料。 扩散阻挡区域适于防止第一导电材料通过扩散阻挡区域的扩散。

公开(公告)号：WO2008058847A1

公开(公告)日：2008-05-22

申请号：PCT/EP2007/061705

申请日：2007-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  GAMBINO, Jeffrey, Peter ,  ADKISSON, James, William ,  SPROGIS, Edmund, Juris ,  RASSEL, Richard, John ,  LEIDY, Robert, Kenneth ,  JAFFE, Mark, David ,  LUCE, Stephen, Ellinwood ,  HE, Zhong-Xiang

Inventor： GAMBINO, Jeffrey, Peter ,  ADKISSON, James, William ,  SPROGIS, Edmund, Juris ,  RASSEL, Richard, John ,  LEIDY, Robert, Kenneth ,  JAFFE, Mark, David ,  LUCE, Stephen, Ellinwood ,  HE, Zhong-Xiang

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2924/00014

Abstract: A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein "m" levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having "n" levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.

Abstract translation: CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个层形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。 具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。 微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。

公开(公告)号：WO2007137049A2

公开(公告)日：2007-11-29

申请号：PCT/US2007/069002

申请日：2007-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BERNSTEIN, Kerry ,  DALTON, Timothy, Joseph ,  GAMBINO, Jeffrey, Peter ,  JAFFE, Mark, David ,  KARTSCHOKE, Paul, David ,  LUCE, Stephen, Ellinwood ,  STAMPER, Anthony, Kendall

Inventor： BERNSTEIN, Kerry ,  DALTON, Timothy, Joseph ,  GAMBINO, Jeffrey, Peter ,  JAFFE, Mark, David ,  KARTSCHOKE, Paul, David ,  LUCE, Stephen, Ellinwood ,  STAMPER, Anthony, Kendall

IPC: H01L23/52 ,  H01L21/44

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon (110A and 110B) from two silicon-on- insulator wafers (110A and 100B), respectively, having devices (130A and 130B), respectively, fabricated therein and bonding them back to back utilizing the buried oxide layers (115). Contacts (210) are then formed in the upper wafer (I00B) to devices (130A) in the lower wafer (100A) and wiring levels (170) are formed on the upper wafer (100B). The lower wafer (100A) may include wiring levels (170). The lower wafer (100A) may include landing pads (230) for the contacts. Contacts to the silicon layer (120) of the lower wafer (100A) may be silicided.

Abstract translation: 一种半导体结构及其制造方法。 该方法包括从分别制造在其中的器件（130A和130B）的两个绝缘体上硅晶片（110A和100​​B）去除后侧硅（110A和110B），并使用掩埋氧化物 层（115）。 接触件（210）然后在上晶片（I00B）中形成到下晶片（100A）中的器件（130A），并且布线级（170）形成在上晶片（100B）上。 下晶片（100A）可以包括布线​​层（170）。 下晶片（100A）可以包括用于触点的着陆焊盘（230）。 与下晶片（100A）的硅层（120）的接触可以被硅化。