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    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION
    3.
    发明申请
    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION 审中-公开
    在半导体制造中去除蚀刻工艺残留

    公开(公告)号：WO2008091923A3

    公开(公告)日：2009-12-30

    申请号：PCT/US2008051758

    申请日：2008-01-23

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    IPC: C11D7/00

    CPC classification number: H01L23/5223 ,  H01L21/02063 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure incl udes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

    Abstract translation: 半导体结构及其形成方法。 半导体制造方法包括提供结构的步骤。 一种结构包括（a）介电层，（b）掩埋在所述电介质层中的第一导电区域，其中所述第一导电区域包括第一导电材料，和（c）第二导电区域， 介电层，其中第二导电区域包括不同于第一导电材料的第二导电材料。 该方法还包括以下步骤：在电介质层中形成第一孔和第二孔，导致第一和第二导电区域分别通过第一孔和第二孔暴露于周围环境。 然后，该方法还包括将碱性溶剂引入第一孔和第二孔的底壁和侧壁的步骤。

    THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE
    4.
    发明申请
    THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE 审中-公开
    通过基础包括可变的平台轮廓

    公开(公告)号：WO2009137313A1

    公开(公告)日：2009-11-12

    申请号：PCT/US2009/042206

    申请日：2009-04-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COONEY, Edward, Crandal ,  LINDGREN, Peter, James ,  OSSENKOP, Dorreen, Jane ,  STAMPER, Anthony, Kendall

    Inventor： COONEY, Edward, Crandal ,  LINDGREN, Peter, James ,  OSSENKOP, Dorreen, Jane ,  STAMPER, Anthony, Kendall

    IPC: H01L21/441 ,  H01L29/417

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture (R1-RA) within a substrate. (16) Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region (R1) at a surface of the substrate; (2) a constricted region contiguous (R2) with the first comparatively wide region; (3) a second comparatively wide region contiguous (R3) with the constricted region; and (4) a tapered region contiguous (R4) with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via.

    Abstract translation: 诸如半导体结构的微电子结构和用于制造微电子结构的方法包括在衬底内的孔（R1-RA）。 （16）进入孔位于并形成通孔。 通孔可以包括通孔基板通孔。 所述孔包括，至少部分地依次连续地进行穿过所述基底：（1）在所述基底的表面处的第一相对较宽的区域（R1） （2）具有第一相对较宽区域的收缩区域连续（R2）; （3）与收缩区域相邻的第二相对宽的区域（R3）; 和（4）与第二较宽区域连续的（R4）的锥形区域。 孔的结构提供了填充孔的容易性以及通孔内的空隙隔离。

    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME
    6.
    发明申请
    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 审中-公开
    通过VIAS的低电阻和电感及其制造方法

    公开(公告)号：WO2007084879A3

    公开(公告)日：2008-02-21

    申请号：PCT/US2007060544

    申请日：2007-01-15

    Applicant: IBM ,  ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/44 ,  H01L21/77

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).

    Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一介电层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述电介质隔离（250）的周边内并且在所述绝缘隔离（250）的周边内并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至小于衬底厚度（001）的深度（D1）。 填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平面化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。

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