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    STRAINED SILICON MOS DEVICE WITH BOX LAYER BETWEEN THE SOURCE AND DRAIN REGIONS
    1.
    发明申请
    STRAINED SILICON MOS DEVICE WITH BOX LAYER BETWEEN THE SOURCE AND DRAIN REGIONS 审中-公开
    在源区和漏区之间应用盒层的应变硅MOS器件

    公开(公告)号：WO2007102870A3

    公开(公告)日：2007-12-06

    申请号：PCT/US2006047139

    申请日：2006-12-06

    Applicant: INTEL CORP ,  CURELLO GIUSEPPE ,  DESHPANDE HEMANT V ,  TYAGI SUNIT ,  BOHR MARK

    Inventor： CURELLO GIUSEPPE ,  DESHPANDE HEMANT V ,  TYAGI SUNIT ,  BOHR MARK

    IPC: H01L21/336 ,  H01L29/165 ,  H01L29/78

    CPC classification number: H01L29/66628 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78687

    Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and suicide spike defects while preventing gate edge junction parasitic capacitance.

    Abstract translation: MOS器件包括栅极叠层，该栅极叠层包括设置在栅极电介质上的栅极电极，形成在栅极叠层的横向相对侧上的第一间隔物和第二间隔物，靠近第一间隔物的源极区域，靠近第二间隔物的漏极区域 间隔体以及沟道区域，所述沟道区域位于栅极叠层的下方并且设置在源极区域和漏极区域之间。 本发明的MOS器件还包括埋置氧化物（BOX）区域，所述埋入氧化物（BOX）区域在沟道区域下方并且设置在源极区域和漏极区域之间。 BOX区域能够形成更深的源极和漏极区域，以减少晶体管电阻和硅化物尖峰缺陷，同时防止栅极边缘结寄生电容。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
    5.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 审中-公开
    形成半导体结构的方法

    公开(公告)号：WO2007003220A1

    公开(公告)日：2007-01-11

    申请号：PCT/EP2005/008199

    申请日：2005-06-30

    Applicant: FREESCALE SEMICONDUCTOR, INC ,  SPARKS, Terry

    Inventor： SPARKS, Terry

    IPC: H01L29/786 ,  H01L21/336 ,  H01L21/3213 ,  H01L21/764

    CPC classification number: H01L29/78639 ,  H01L21/32135 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78654

    Abstract: A method of forming a semiconductor structure comprises forming a first layer of silicon (10) and then forming a second, silicon germanium, layer (12) adjacent the silicon layer (10). A thin third layer of silicon (14) is then formed adjacent the second layer (12). A gate structure is then formed upon the third layer of silicon (14) using convention Complementary Metal Oxide Semiconductor (CMOS) processes. Trenches are then formed into the second layer (12) and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On­-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls (28) from silicon nitride, the silicon nitride (30) also filling a cavity formed beneath the third layer of silicon (14) by removal of the silicon germanium.

    Abstract translation: 形成半导体结构的方法包括形成第一层硅（10），然后形成邻近硅层（10）的第二硅锗层（12）。 然后在第二层（12）附近形成薄的第三层硅（14）。 然后使用常规的互补金属氧化物半导体（CMOS）工艺在第三层硅（14）上形成栅极结构。 然后将沟槽形成第二层（12），然后将该结构暴露于热的气体化学蚀刻剂，例如加热的盐酸。 蚀刻剂除去硅锗，从而形成无硅结构。 此后，应用常规CMOS处理技术来完成作为金属氧化物半导体场效应晶体管的结构，包括从氮化硅形成间隔壁（28），氮化硅（30）还填充形成在第三层下面的空腔 硅（14）通过去除硅锗。

    STRAINED SILICON MOS DEVICE WITH BOX LAYER BETWEEN THE SOURCE AND DRAIN REGIONS
    6.
    发明申请
    STRAINED SILICON MOS DEVICE WITH BOX LAYER BETWEEN THE SOURCE AND DRAIN REGIONS 审中-公开
    源区和排水区之间的带有硅层的应变硅MOS器件

    公开(公告)号：WO2007102870A2

    公开(公告)日：2007-09-13

    申请号：PCT/US2006/047139

    申请日：2006-12-06

    Applicant: INTEL CORPORATION ,  CURELLO, Giuseppe ,  DESHPANDE, Hemant, V. ,  TYAGI, Sunit ,  BOHR, Mark

    Inventor： CURELLO, Giuseppe ,  DESHPANDE, Hemant, V. ,  TYAGI, Sunit ,  BOHR, Mark

    CPC classification number: H01L29/66628 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78687

    Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and suicide spike defects while preventing gate edge junction parasitic capacitance.

    Abstract translation: MOS器件包括栅极堆叠，其包括设置在栅极电介质上的栅极电极，形成在栅极堆叠的横向相对侧上的第一间隔物和第二间隔物，靠近第一间隔物的源极区域，靠近第二间隔区的漏极区域 间隔物和位于栅叠层下方的沟道区，并设置在源区和漏区之间。 本发明的MOS器件还包括在沟道区域的下方并设置在源极区域和漏极区域之间的掩埋氧化物（BOX）区域。 BOX区域可以形成更深的源极和漏极区域，以减少晶体管电阻和硅化物尖峰缺陷，同时防止栅极边缘结的寄生电容。

    METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM
    8.
    发明申请
    METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM 审中-公开
    使用硅锗制备半导体结构的方法

    公开(公告)号：WO2005117101A2

    公开(公告)日：2005-12-08

    申请号：PCT/US2005/012391

    申请日：2005-04-13

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ORLOWSKI, Marius K. ,  LIU, Chun-Li ,  YEAP, Choh-Fei

    Inventor： ORLOWSKI, Marius K. ,  LIU, Chun-Li ,  YEAP, Choh-Fei

    IPC: H01L21/8234

    CPC classification number: H01L29/0847 ,  H01L29/1033 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78606 ,  H01L29/78639 ,  H01L29/78687

    Abstract: Silicon carbon is used as a diffusion barrier (18,108) to germanium so that a silicon layer (20,110) can be subsequently formed without being contaminated with germanium. This is useful in separating silicon layers (20, 110) from silicon germanium layers (16,106) in situations in which both silicon and silicon germanium are desired to be present on the same semiconductor device (10) such as for providing different materials for optimizing carrier mobility between N and P channel transistors (27) and for a raised source/drain (134,136) of silicon in the case of a silicon germanium body.

    Abstract translation: 硅碳用作锗的扩散阻挡层（18,108），从而随后可以形成硅层（20,110），而不会被锗污染。 在需要在同一半导体器件（10）上存在硅和硅锗的情况下，例如为了提供用于优化载体的不同材料的情况，这可用于在硅层（20,110）与硅锗层（16,106）之间分离硅层 在硅锗体的情况下，N沟道晶体管（P沟道晶体管）和P沟道晶体管（27）之间的迁移率以及硅的升高的源极/漏极（134,136）的迁移率。

    LOW-POWER MULTIPLE-CHANNEL FULLY DEPLETED QUANTUM WELL CMOSFETS
    10.
    发明申请
    LOW-POWER MULTIPLE-CHANNEL FULLY DEPLETED QUANTUM WELL CMOSFETS 审中-公开
    低功耗多通道全通道量子阱CMOSFETs

    公开(公告)号：WO2005053035A1

    公开(公告)日：2005-06-09

    申请号：PCT/US2004/033413

    申请日：2004-10-08

    Applicant: ADVANCED MICRO DEVICES, INC. ,  PAN, James, N. ,  PELLERIN, John, G. ,  CHEEK, Jon, D.

    Inventor： PAN, James, N. ,  PELLERIN, John, G. ,  CHEEK, Jon, D.

    IPC: H01L29/786

    CPC classification number: H01L29/78696 ,  H01L29/78639

    Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions (15) are provided on a substrate (12) with a gate electrode (16) formed on the uppermost channel region (15), separated by a gate oxide (14c), for example. The vertical stacking of multiple channels (15) and the gate electrode (16) permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

    Abstract translation: 多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。 多个通道区域（15）设置在基板（12）上，其栅极电极（16）形成在最上通道区域（15）上，例如由栅极氧化物（14c）分开。 多个通道（15）和栅电极（16）的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

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