公开(公告)号：WO2017165027A1

公开(公告)日：2017-09-28

申请号：PCT/US2017/018211

申请日：2017-02-16

申请人： SANDISK TECHNOLOGIES LLC

发明人： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  KANAKAMEDALA, Senaka ,  ZHOU, Fei ,  PERI, Somesh ,  TSUTSUMI, Masanori ,  SHUKLA, Keerti ,  IKAWA, Yusuke ,  SAKAKIBARA, Kyohiko ,  TAKII, Eisuke

IPC分类号： H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

CPC分类号： H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

摘要翻译： 存储器开口可以通过设置在衬底上的绝缘层和牺牲材料层的交替堆叠来形成。 环形蚀刻停止材料部分设置在存储器开口周围的牺牲材料层的每一层处。 环形蚀刻停止材料部分可通过将牺牲材料层的表面部分转换成电介质材料部分或通过围绕存储器开口凹陷牺牲材料层并在记忆开口周围填充凹痕来形成。 在形成存储器堆叠结构之后，从背面去除牺牲材料层。 环形蚀刻停止材料部分至少部分地被转换以形成电荷捕捉材料部分。 在存储器堆叠结构周围彼此垂直隔开电荷捕捉材料部分使得位于不同字线水平的电​​荷捕捉材料部分之间的泄漏最小化。

公开(公告)号：WO2016191156A4

公开(公告)日：2017-02-16

申请号：PCT/US2016032928

申请日：2016-05-17

申请人： SANDISK TECHNOLOGIES LLC

发明人： RABKIN PETER ,  PACHAMUTHU JAYAVEL ,  ALSMEIER JOHANN ,  HIGASHITANI MASAAKI

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7926

摘要： A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to S13N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.

摘要翻译： 公开了具有高k电荷存储区域的存储单元以及制造方法的非易失性存储装置。 电荷存储区域具有三层或更多层介电材料。 至少一层是高k材料。 与S13N4相比，高k层具有更高的陷阱密度。 电荷存储区域中的高k电介质增强了与存储单元通道的电容耦合，这可以提高存储单元电流，编程速度和擦除速度。 电荷存储区具有高 - 低 - 高导带偏移，这可以改善数据保留。 电荷存储区域具有低 - 高 - 低价带偏移，这可以改善擦除。

公开(公告)号：WO2017019177A1

公开(公告)日：2017-02-02

申请号：PCT/US2016/036086

申请日：2016-06-06

申请人： SANDISK TECHNOLOGIES LLC

发明人： KANAKAMEDALA, Senaka ,  MAKALA, Raghuveer S. ,  ZHANG, Yanli ,  LEE, Yao-Sheng ,  MATAMIS, George

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7926

摘要： An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.

摘要翻译： 在衬底上形成交替堆叠的绝缘层和牺牲材料层。 分离器绝缘体结构可以可选地通过交替堆叠形成。 通过交替堆叠形成存储器开口，并且牺牲材料层被选择性地去除绝缘层。 通过沉积至少一种导电材料，在侧向凹槽中形成导电层。 通过至少沉积半导体材料并引起半导体材料与导电层和/或牺牲金属层的材料的反应，将金属 - 半导体合金区附加到导电层。 存储器堆叠结构可以形成在存储器开口中，并且直接在导电层的金属 - 半导体合金区域上形成。

公开(公告)号：WO2016200742A1

公开(公告)日：2016-12-15

申请号：PCT/US2016/036083

申请日：2016-06-06

申请人： SANDISK TECHNOLOGIES LLC

发明人： RABKIN, Peter ,  PACHAMUTHU, Jayavel ,  ALSMEIER, Johann ,  HIGASHITANI, Masaaki

IPC分类号： H01L27/115 ,  H01L29/205

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7889 ,  H01L29/7926

摘要： A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

摘要翻译： 限制在二维圆柱形区域内的圆柱形约束电子气体可以形成在延伸穿过包括控制栅电极的多个导电层的垂直半导体沟道中。 存储器开口中的记忆膜插入在垂直半导体沟道和导电层之间。 垂直半导体沟道包括较宽的带隙半导体材料和窄带隙半导体材料。 在较宽带隙半导体材料和窄带隙半导体材料之间的界面处形成圆柱形约束电子气。 作为二维电子气体，圆柱形约束电子气体可以为垂直半导体通道提供高电荷载流子迁移率，其可有利地用于为三维存储器件提供更高的性能。

公开(公告)号：WO2015161569A1

公开(公告)日：2015-10-29

申请号：PCT/CN2014/081926

申请日：2014-07-10

申请人： 中国科学院微电子研究所

发明人： 霍宗亮

IPC分类号： H01L21/8239

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/7887 ,  H01L29/7889 ,  H01L29/7926

摘要： 一种三维半导体器件，包括多个存储单元和多个选择晶体管，所述多个存储单元的每一个包括：沟道层，沿垂直于衬底表面的方向分布；多个层间绝缘层与多个栅极堆叠结构，沿着所述沟道层的侧壁交替层叠；多个浮栅，位于所述多个层间绝缘层与所述沟道层的侧壁之间；漏极，位于所述沟道层的顶部；以及源极，位于所述多个存储单元的相邻两个存储单元之间的所述衬底中。上述三维半导体器件及其制造方法，在垂直沟道侧壁植入浮栅，通过栅电极与浮栅之间的耦合控制垂直沟道侧壁上感应生成的源漏区的开启，有效提高了源漏区的感应效率和强度，减小了存储单元的源漏电阻，从而提高了存储阵列的读取电流和读取速度。

公开(公告)号：WO2015126664A1

公开(公告)日：2015-08-27

申请号：PCT/US2015/015155

申请日：2015-02-10

申请人： SANDISK TECHNOLOGIES, INC.

发明人： PACHAMUTHU, Jayavel ,  ALSMEIER, Johann ,  CHIEN, Henry

IPC分类号： H01L27/115

CPC分类号： H01L27/11556 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L29/7926

摘要： A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.

摘要翻译： 包括第一导电层和第一电绝缘层的交替层的第一叠层形成有第一台阶表面和其上的第一介电材料部分。 可以通过第一台阶表面形成包括电介质金属氧化物的介质柱结构。 可以形成下部存储器开口，并且填充有包括下部半导体沟道和掺杂半导体区域的一次性材料或下部存储器开口结构。 可以顺序地形成至少一个介电材料层和包括第二导电层和第二电绝缘层的交替层的第二堆叠。 上存储器开口可以通过第二堆叠和至少一个电介质材料层形成。 可以在去除一次性材料之后形成记忆膜和半导体通道，或者可以在掺杂半导体区域上形成上半导体沟道。

公开(公告)号：WO2015105599A1

公开(公告)日：2015-07-16

申请号：PCT/US2014/068287

申请日：2014-12-03

申请人： MICRON TECHNOLOGY, INC.

发明人： KARDA, Kamal, M. ,  MOULI, Chandra ,  SANDHU, Gurtej, S.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/2454 ,  H01L21/02568 ,  H01L27/11582 ,  H01L27/2463 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/7926 ,  H01L45/065 ,  H01L45/141 ,  H01L45/16

摘要： In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 A to less than or equal to about Ι θΑ; and/or has a thickness of from 1 monolayer to 7 monolayers.

摘要翻译： 在一些实施例中，晶体管包括具有底部源极/漏极区域，第一绝缘材料，导电栅极，第二绝缘材料和顶部源极/漏极区域的堆叠。 该堆叠具有沿着底部源极/漏极区域具有底部的垂直侧壁，沿着导电栅极的中间部分和沿着顶部源极/漏极区域的顶部部分。 第三绝缘材料沿着垂直侧壁的中间部分。 通道区域材料沿着第三绝缘材料。 通道区域材料直接抵靠垂直侧壁的顶部和底部。 沟道区域材料具有在大于约3至小于或等于约10的范围内的厚度; 和/或具有1个单层至7个单层的厚度。

公开(公告)号：WO2014165397A1

公开(公告)日：2014-10-09

申请号：PCT/US2014/032123

申请日：2014-03-28

申请人： SANDISK TECHNOLOGIES, INC.

发明人： MAKALA, Raghuveer S. ,  LEE, Yao-Sheng ,  ALSMEIER, Johann ,  CHIEN, Henry ,  TERAHARA, Masanori ,  WATATANI, Hirofumi

IPC分类号： H01L27/115

CPC分类号： H01L29/66833 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening extending partially through the stack and forming a masking layer on a sidewall and bottom surface of the at least one opening. The method also includes removing the masking layer from the bottom surface of the at least one opening while leaving the masking layer on the sidewall of the at least one opening, and further etching the at least one opening to extend the at least one opening further through the stack while the masking layer remains on the sidewall of the at least one opening.

摘要翻译： 制造半导体器件的方法包括在衬底上形成第一材料和第二材料的交替层的叠层，蚀刻叠层以形成部分延伸穿过叠层的至少一个开口，并在侧壁和底部上形成掩蔽层 至少一个开口的表面。 该方法还包括从至少一个开口的底表面移除掩模层，同时将掩模层留在至少一个开口的侧壁上，并进一步蚀刻至少一个开口以将至少一个开口进一步延伸通过 该掩模层保留在该至少一个开口的侧壁上。

公开(公告)号：WO2014164062A1

公开(公告)日：2014-10-09

申请号：PCT/US2014/020290

申请日：2014-03-04

申请人： SANDISK TECHNOLOGIES, INC.

发明人： MAKALA, Raghuveer S. ,  LEE, Yao-Sheng ,  PACHAMUTHU, Jayavel ,  ALSMEIER, Johann ,  CHIEN, Henry

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/822 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

摘要翻译： 制造垂直NAND器件的方法包括在衬底上形成存储器堆叠的下部，在存储堆的下部形成存储器开口的下部，并至少部分地填充存储器开口的下部， 牺牲材料。 该方法还包括在存储器堆叠的下部并在牺牲材料的上方形成存储器堆叠的上部，在存储器堆叠的上部形成存储器开口的上部部分，以将下部的牺牲材料露出 部分存储器开口，去除牺牲材料以将存储器开口的下部与存储器开口的相应上部连接以形成连续的存储器开口，并在每个连续的存储器开口中形成半导体通道。

公开(公告)号：WO2014123660A1

公开(公告)日：2014-08-14

申请号：PCT/US2014/011228

申请日：2014-01-13

申请人： MICRON TECHNOLOGY, INC.

发明人： THIMMEGOWDA, Deepak ,  CLEEREMAN, Brian ,  HASNAT, Khaled

IPC分类号： H01L27/15

CPC分类号： H01L27/11556 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.

摘要翻译： 3-D存储器阵列包括多个高度延伸的存储器单元串。 选择装置的阵列是垂直于多个单独的弦与单独的连接。 选择装置分别包括通道，靠近通道的栅极电介质和靠近栅极电介质的栅极材料。 各个通道彼此间隔开。 栅极材料包括多个栅极线，这些栅极线沿垂直于串的间隔通道的列延伸。 介电材料横向位于紧邻栅极线之间。 介电材料和栅极线在界面处彼此具有纵向非线性边缘。 公开了另外的实施例。