公开(公告)号：WO2005065385A3

公开(公告)日：2005-07-21

申请号：PCT/US2004/043965

申请日：2004-12-29

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  CHALLA, Ashok ,  ELBANHAWY, Alan ,  GREBS, Thomas E. ,  KOCON, Christopher B. ,  KRAFT, Nathan L. ,  PROBST, Dean E. ,  RIDLEY, Rodney S. ,  SAPP, Steven P. ,  WANG, Qi ,  WILSON, Peter H. ,  YEDINAK, Joseph A. ,  YUN, Chongman ,  JUNG, Jin-young ,  JANG, Ho-cheol ,  STOKES, Richard ,  DOLNY, Gary M. ,  MYTYCH, John ,  LOSEE, Becky ,  SELSLEY, Adam ,  HERRICK, Robert ,  MURPHY, James J. ,  MADSON, Gordon K. ,  WOOLSEY, Debra S. ,  MARCHANT, Bruce D. ,  REXER, Christopher L ,  SANI, Babak S. ,  LEE, Jae-Gil

Inventor： CHALLA, Ashok ,  ELBANHAWY, Alan ,  GREBS, Thomas E. ,  KOCON, Christopher B. ,  KRAFT, Nathan L. ,  PROBST, Dean E. ,  RIDLEY, Rodney S. ,  SAPP, Steven P. ,  WANG, Qi ,  WILSON, Peter H. ,  YEDINAK, Joseph A. ,  YUN, Chongman ,  JUNG, Jin-young ,  JANG, Ho-cheol ,  STOKES, Richard ,  DOLNY, Gary M. ,  MYTYCH, John ,  LOSEE, Becky ,  SELSLEY, Adam ,  HERRICK, Robert ,  MURPHY, James J. ,  MADSON, Gordon K. ,  WOOLSEY, Debra S. ,  MARCHANT, Bruce D. ,  REXER, Christopher L ,  SANI, Babak S. ,  LEE, Jae-Gil

IPC: H01L29/78

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronics are disclosed. One aspect of the invention combines a number of charge balancing techniques (311) and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices (300B) with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices (300B) are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches (300, 302), formation of dielectric layers inside trenches (301, 302), formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices (300B) incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device (300B) and provide improvements to the packaging of charge balanced power devices.

公开(公告)号：WO2012149195A1

公开(公告)日：2012-11-01

申请号：PCT/US2012/035262

申请日：2012-04-26

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  YEDINAK, Josph A. ,  REXER, Christopher L. ,  RINEHIMER, Mark L. ,  SHENOY, Praveen Muraleedharan ,  LEE, Jaegil ,  YILMAZ, Hamza ,  YUN, Chongman ,  REICHL, Dwayne S. ,  PAN, James ,  RIDLEY, Rodney S. ,  HEIDENREICH, Harold

Inventor： YEDINAK, Josph A. ,  REXER, Christopher L. ,  RINEHIMER, Mark L. ,  SHENOY, Praveen Muraleedharan ,  LEE, Jaegil ,  YILMAZ, Hamza ,  YUN, Chongman ,  REICHL, Dwayne S. ,  PAN, James ,  RIDLEY, Rodney S. ,  HEIDENREICH, Harold

IPC: H01L29/872

CPC classification number: H01L29/7811 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract translation: 功率器件包括半导体区域，该半导体区域又包括多个交替布置的第一和第二导电类型的柱。 第二导电类型的多个柱中的每一个还包括沿着第二导电类型的柱的深度彼此顶部布置的多个第二导电类型的注入区，以及填充有第二导电类型的半导体材料的沟槽部 在第二导电类型的多个植入区域的正上方。

公开(公告)号：WO2008014391A3

公开(公告)日：2008-01-31

申请号：PCT/US2007/074460

申请日：2007-07-26

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  YEDINAK, Joseph, A. ,  WOODIN, Richard, L. ,  REXER, Christopher, L. ,  SHENOY, Praveen, Muraleedharan ,  OH, Kwanghoon ,  YUN, Chongman

Inventor： YEDINAK, Joseph, A. ,  WOODIN, Richard, L. ,  REXER, Christopher, L. ,  SHENOY, Praveen, Muraleedharan ,  OH, Kwanghoon ,  YUN, Chongman

IPC: H01L21/331 ,  H01L31/111

Abstract: A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes 255-260. or a PNP transistor 205, across the blocking junction of a wide bandgap device 210 or 250.

公开(公告)号：WO2009039441A1

公开(公告)日：2009-03-26

申请号：PCT/US2008/077118

申请日：2008-09-19

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  YEDINAK, Joseph, A. ,  LEE, Jaegil ,  JANG, Hocheol ,  YUN, Chongman ,  SHENOY, Praveen Muraleedharan ,  REXER, Christopher, L. ,  KIM, Changwook ,  LEE, Jonghun ,  HIGGS, Jason, M. ,  REICHL, Dwayne, S. ,  SHARP, Joelle ,  WANG, Qi ,  KIM, Yongsub ,  LEE, Jungkil ,  RINEHIMER, Mark, L. ,  JUNG, Jinyoung

Inventor： YEDINAK, Joseph, A. ,  LEE, Jaegil ,  JANG, Hocheol ,  YUN, Chongman ,  SHENOY, Praveen Muraleedharan ,  REXER, Christopher, L. ,  KIM, Changwook ,  LEE, Jonghun ,  HIGGS, Jason, M. ,  REICHL, Dwayne, S. ,  SHARP, Joelle ,  WANG, Qi ,  KIM, Yongsub ,  LEE, Jungkil ,  RINEHIMER, Mark, L. ,  JUNG, Jinyoung

IPC: H01L29/00

CPC classification number: H01L29/66712 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1075 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power device includes an active region and a termination region surrounding the active region. A plurality of pillars of first and second conductivity type are alternately arranged in each of the active and termination regions. The pillars of first conductivity type in the active and termination regions have substantially the same width, and the pillars of second conductivity type in the active region have a smaller width than the pillars of second conductivity type in the termination region so that a charge balance condition in each of the active and termination regions results in a higher breakdown voltage in the termination region than in the active region.

Abstract translation: 功率器件包括有源区和围绕有源区的端接区。 多个第一和第二导电类型的柱交替布置在每个有源端子区域和端接区域中。 在有源和终端区域中的第一导电类型的柱具有基本上相同的宽度，并且有源区中的第二导电类型的柱具有比端接区域中的第二导电类型的柱小的宽度，使得电荷平衡条件 在每个有源和终止区域中，终端区域中的击穿电压高于有源区域。

公开(公告)号：WO2005091799A3

公开(公告)日：2006-09-28

申请号：PCT/US2005004122

申请日：2005-02-08

Applicant: FAIRCHILD SEMICONDUCTOR ,  CALAFUT DANIEL ,  REXER CHRISTOPHER L

Inventor： CALAFUT DANIEL ,  REXER CHRISTOPHER L

IPC: H01L29/80 ,  H01L29/78 ,  H01L21/336 ,  H01L29/872

CPC classification number: H01L29/8725 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7806 ,  H01L29/7813

Abstract: In accordance with the present invention, a monolithically integrated structure combines a field effect transistor and a Schottky structure in an active area of a semiconductor substrate. The field effect transistor includes a first trench extending into the substrate and substantially filled by conductive material forming a gate electrode of the field effect transistor. A pair of doped source regions are positioned adjacent to and on opposite sides of the trench and inside a doped body region. The Schottky structure includes a pair of adjacent trenches extending into the substrate. Each of the pair of adjacent trenches is substantially filled by a conductive material which is separated from trench side-walls by a thin layer of dielectric. The Schottky structure consumes 2.5% to 5.0% of the active area, and the field effect transistor consumes the remaining portion of the active area.

Abstract translation: 根据本发明，单片集成结构在半导体衬底的有源区域中组合场效应晶体管和肖特基结构。 场效应晶体管包括延伸到衬底中并且基本上由形成场效应晶体管的栅电极的导电材料填充的第一沟槽。 一对掺杂源极区域邻近沟槽的相对侧并且位于掺杂体区域的内侧。 肖特基结构包括延伸到衬底中的一对相邻沟槽。 一对相邻沟槽中的每一个基本上由导电材料填充，导电材料通过薄的电介质层与沟槽侧壁分离。 肖特基结构消耗有效面积的2.5％至5.0％，场效应晶体管消耗有源区域的剩余部分。

公开(公告)号：WO2008014391A2

公开(公告)日：2008-01-31

申请号：PCT/US2007074460

申请日：2007-07-26

Applicant: FAIRCHILD SEMICONDUCTOR ,  YEDINAK JOSEPH A ,  WOODIN RICHARD L ,  REXER CHRISTOPHER L ,  SHENOY PRAVEEN MURALEEDHARAN ,  OH KWANGHOON ,  YUN CHONGMAN

Inventor： YEDINAK JOSEPH A ,  WOODIN RICHARD L ,  REXER CHRISTOPHER L ,  SHENOY PRAVEEN MURALEEDHARAN ,  OH KWANGHOON ,  YUN CHONGMAN

IPC: H01L21/00 ,  H01L31/0312

CPC classification number: H01L29/872 ,  H01L27/0248 ,  H01L29/1608 ,  H01L29/8618 ,  H01L29/87

Abstract: A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.

Abstract translation: 一种用于在抑制电压瞬变期间保护宽带隙器件不发生故障的方法和装置。 通过在宽带隙器件的阻塞结上放置一个或多个二极管或PNP晶体管来实现雪崩能力的改善。

公开(公告)号：WO2005091799A2

公开(公告)日：2005-10-06

申请号：PCT/US2005/004122

申请日：2005-02-08

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION ,  CALAFUT, Daniel ,  REXER, Christopher, L.

Inventor： CALAFUT, Daniel ,  REXER, Christopher, L.

IPC: H01L29/80

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7806 ,  H01L29/8725

Abstract: In accordance with the present invention, a monolithically integrated structure combines a field effect transistor and a Schottky structure in an active area of a semiconductor substrate. The field effect transistor includes a first trench extending into the substrate and substantially filled by conductive material forming a gate electrode of the field effect transistor. A pair of doped source regions are positioned adjacent to and on opposite sides of the trench and inside a doped body region. The Schottky structure includes a pair of adjacent trenches extending into the substrate. Each of the pair of adjacent trenches is substantially filled by a conductive material which is separated from trench side-walls by a thin layer of dielectric. The Schottky structure consumes 2.5% to 5.0% of the active area, and the field effect transistor consumes the remaining portion of the active area.

Abstract translation: 根据本发明，单片集成结构在半导体衬底的有源区域中组合场效应晶体管和肖特基结构。 场效应晶体管包括延伸到衬底中并且基本上由形成场效应晶体管的栅电极的导电材料填充的第一沟槽。 一对掺杂源极区域邻近沟槽的相对侧并且位于掺杂体区域的内侧。 肖特基结构包括延伸到衬底中的一对相邻沟槽。 一对相邻沟槽中的每一个基本上由导电材料填充，导电材料通过薄的电介质层与沟槽侧壁分离。 肖特基结构消耗有源面积的2.5％至5.0％，场效应晶体管消耗有源区的剩余部分。