公开(公告)号：WO2016200971A1

公开(公告)日：2016-12-15

申请号：PCT/US2016/036482

申请日：2016-06-08

Applicant: SYNOPSYS, INC.

Inventor： MOROZ, Victor ,  HUANG, Joanne ,  KAWA, Jamil

IPC: H01L29/78

CPC classification number: H01L29/78696 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/151 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66742 ,  H01L29/7391 ,  H01L29/778 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/7854

Abstract: Roughly described, a transistor is formed with a semiconductor 2D material layer wrapped conformally on at least part of a 3D structure. The 3D structure can be for example a ridge made of a dielectric material, or made of dielectric material alternating longitudinally with a semiconductive or conductive material. Alternatively the 3D structure can be tree-shaped. Other shapes are possible as well. Aspects also include methods for making such structures, as well as integrated circuit layouts defining such structures and methods for developing such layouts, a machine readable data storage medium storing design entries which include some which define such structures and layouts, methods for developing such design entries. Aspects further include corrugated wafers which are prepared as an intermediate product for use in fabricating integrated circuits having a semiconductor 2D material layer disposed conformally on a 3D structure.

Abstract translation: 粗略地描述，晶体管形成有半导体2D材料层，其保形地包裹在3D结构的至少一部分上。 3D结构可以是例如由电介质材料制成的脊，或由与半导体或导电材料纵向交替的电介质材料制成的脊。 或者，3D结构可以是树状的。 其他形状也是可能的。 方面还包括制造这种结构的方法以及定义用于开发这种布局的这种结构和方法的集成电路布局，存储设计条目的机器可读数据存储介质，其包括限定这种结构和布局的一些，用于开发这样的设计条目的方法 。 方面还包括作为中间产品制备的波纹晶片，其用于制造具有共面设置在3D结构上的半导体2D材料层的集成电路。

公开(公告)号：WO2015094301A1

公开(公告)日：2015-06-25

申请号：PCT/US2013/076651

申请日：2013-12-19

Applicant: INTEL CORPORATION ,  KIM, Seiyon ,  RIOS, Rafael ,  FERDOUSI, Fahmida ,  KUHN, Kelin, J.

Inventor： KIM, Seiyon ,  RIOS, Rafael ,  FERDOUSI, Fahmida ,  KUHN, Kelin, J.

IPC: H01L21/336

CPC classification number: H01L29/7853 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0684 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

Abstract translation: 描述了具有基于混合几何的有源区域的非平面半导体器件。 例如，半导体器件包括混合沟道区域，其包括设置在鳍状FET部分上方的Ω-FET部分上方的纳米线部分。 栅极叠层设置在混合沟道区域的暴露表面上。 栅极堆叠包括栅极电介质层和设置在栅极介电层上的栅电极。 源极和漏极区域设置在混合沟道区域的两侧。

公开(公告)号：WO2014026307A1

公开(公告)日：2014-02-20

申请号：PCT/CN2012/001378

申请日：2012-10-12

Applicant: 中国科学院微电子研究所

Inventor： 马小龙 ,  殷华湘 ,  许森 ,  朱慧珑

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/15 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/151 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/7781 ,  H01L29/785 ,  H01L29/7853

Abstract: 一种半导体器件制造方法，包括：在衬底（10）上形成多个鳍片（13），其中鳍片（13）沿第一方向延伸并且具有类菱形截面；在每个鳍片（13）上形成栅极堆叠结构（30A/30B），栅极堆叠结构（30A/30B）横跨多个鳍片（13）并且沿第二方向延伸；其中，每个鳍片（13）中位于栅极堆叠结构（30A/30B）下方的部分构成器件的沟道区（1C），每个鳍片（13）中位于栅极堆叠结构（30A/30B）沿第一方向的两侧的部分构成源漏区（1S、1D）。采用类菱形鳍片（13）提高了栅控能力以有效抑制短沟道效应，此外利用外延量子阱（20）更好地限制载流子、提高了器件驱动能力。

公开(公告)号：WO2013095341A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/065914

申请日：2011-12-19

Applicant: INTEL CORPORATION ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  DEWEY, Gilbert ,  MUKHERJEE, Niloy ,  KAVALIEROS, Jack ,  RACHMADY, Willy ,  LE, Van ,  CHU-KUNG, Benjamin ,  METZ, Matthew V. ,  CHAU, Robert

Inventor： RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  DEWEY, Gilbert ,  MUKHERJEE, Niloy ,  KAVALIEROS, Jack ,  RACHMADY, Willy ,  LE, Van ,  CHU-KUNG, Benjamin ,  METZ, Matthew V. ,  CHAU, Robert

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Abstract translation: 在同一衬底（例如硅）上的非均质材料如III-V族半导体材料和IV族半导体（例如Ge）共同整合的体系结构和技术。 在实施例中，采用具有交替的纳米线和牺牲层的多层非均相半导体材料堆叠以释放纳米线并允许形成完全包围纳米线晶体管的沟道区域的同轴栅极结构。 在实施例中，各个PMOS和NMOS沟道半导体材料与具有交替的Ge / III-V层的覆盖层的起始衬底共同整合。 在实施例中，单个PMOS和单独NMOS器件内的多个堆叠的纳米线的垂直积分能够为给定的布局区域提供显着的驱动电流。

公开(公告)号：WO2008116210A1

公开(公告)日：2008-09-25

申请号：PCT/US2008/057964

申请日：2008-03-24

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  HUFFMAN, Craig, Henry ,  XIONG, Weize ,  CLEAVELIN, Cloves, Rinn

Inventor： HUFFMAN, Craig, Henry ,  XIONG, Weize ,  CLEAVELIN, Cloves, Rinn

IPC: H01L27/00 ,  H01L29/772

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: One embodiment of the invention relates to a method of fabricating a multi-gate transistor (200). During the method a second gate electrode (202) material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.

Abstract translation: 本发明的一个实施例涉及一种制造多栅极晶体管（200）的方法。 在该方法期间，从形成多栅极晶体管的半导体结构中选择性地去除第二栅电极（202）材料，从而暴露第一栅电极材料的至少一个表面。 第一栅电极材料的暴露表面被去角质化。 随后，去除第一栅电极材料。 还公开了其它方法和装置。

公开(公告)号：WO2008026859A1

公开(公告)日：2008-03-06

申请号：PCT/KR2007/004111

申请日：2007-08-27

Applicant: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION ,  LEE, Jong Ho

Inventor： LEE, Jong Ho

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Provided is a fin field effect transistor (FinFET) having low leakage current and a method of manufacturing the same. The FinFET includes: a bulk silicon substrate! a fence-shaped body formed by patterning the substrate; an insulating layer formed on a surface of the substrate to a first height of the fence-shaped body! a gate insulating layer formed at side walls and an upper surface of the fence-shaped body at which the insulating layer is not formed; a gate electrode formed on the gate insulating layer; source/drain formed at regions of the fence-shaped body where the gate electrode is not formed. The gate electrode includes first and second gate electrodes which are in contact with each other and have different work functions. Particularly, the second gate electrode having a low work function is disposed to be close to the drain. As a result, the FinFET according to the present invention increases a threshold voltage by using a material having the high work function for the gate electrode and lowers the work function of the gate electrode overlapping with the drain, so that gate induced drain leakage (GIDL) can be reduced.

Abstract translation: 提供了具有低漏电流的鳍式场效应晶体管（FinFET）及其制造方法。 FinFET包括：散装硅衬底！ 通过图案化基板形成的栅栏体; 绝缘层，形成在所述基板的表面上至所述栅栏体的第一高度！ 在侧壁形成的栅极绝缘层和不形成绝缘层的栅栏状体的上表面; 形成在所述栅极绝缘层上的栅电极; 源极/漏极形成在栅极体的不形成栅电极的区域处。 栅电极包括彼此接触并具有不同功函数的第一和第二栅电极。 特别地，具有低功函数的第二栅电极设置成靠近漏极。 结果，根据本发明的FinFET通过使用具有用于栅电极的高功函数的材料来增加阈值电压，并降低与漏极​​重叠的栅电极的功函数，从而导致漏极漏极（GIDL ）可以减少。

公开(公告)号：WO2007002426A2

公开(公告)日：2007-01-04

申请号：PCT/US2006024516

申请日：2006-06-20

Applicant: INTEL CORP ,  BRASK JUSTIN ,  KAVALIEROS JACK ,  DOYLE BRIAN ,  SHAH UDAY ,  DATTA SUMAN ,  MAJUMDAR AMLAN ,  CHAU ROBERT

Inventor： BRASK JUSTIN ,  KAVALIEROS JACK ,  DOYLE BRIAN ,  SHAH UDAY ,  DATTA SUMAN ,  MAJUMDAR AMLAN ,  CHAU ROBERT

IPC: H01L21/306 ,  H01L21/336 ,  H01L21/84 ,  H01L29/786

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract translation: 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：WO1997016854A1

公开(公告)日：1997-05-09

申请号：PCT/EP1996004755

申请日：1996-11-01

Applicant: AMO GMBH ,  GONDERMANN, Jörg ,  ROSKOS, Hartmut ,  RÖWER, Thomas ,  KURZ, Heinrich ,  SPANGENBERG, Bernd

Inventor： AMO GMBH

IPC: H01L29/786

CPC classification number: H01L29/7853 ,  H01L29/66795 ,  H01L31/0288 ,  H01L31/03529 ,  Y02E10/50

Abstract: The invention concerns a semiconductor component and a method of manufacturing the same in planar technology, the component comprising a substrate (1), in particular a silicon substrate, and formed thereon mutually spaced isolated connection areas (A), between which an electrically conductive channel area (K) is formed such that it is isolated from these connection areas (A). According to the invention, in order to permit further integration without impairing the electrical parameters with respect to components manufactured in a conventional manner, the three-dimensional channel area (K) formed between the connection areas (A) is prismatic and its cross-sectional area has at least three corners. One of the lateral surfaces of the prism is disposed parallel to the substrate plane.

Abstract translation: 本发明涉及一种装置和用于在平面技术制造半导体器件，其包括衬底（1）的方法，特别是硅衬底，并且在其上形成间隔开的绝缘末端区域（A），在它们之间分离在所述连接区域（A） 导电沟道区域中形成（K）。 以允许进一步的集成，而没有与常规制造的部件相比，恶化的电特性，它提供的是，连接区域延伸的三维地形成沟道区（A）（K）之间延伸有一个棱镜的横截面面积具有至少三个角部的形状， 其中，所述棱镜边缘表面中的一个是平行于基板平面。

公开(公告)号：WO2016079650A1

公开(公告)日：2016-05-26

申请号：PCT/IB2015/058830

申请日：2015-11-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： YAMAZAKI, Shunpei ,  TSUTSUI, Kazuhiro ,  MATSUDA, Shinpei

IPC: H01L29/786 ,  C23C14/08 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/146

CPC classification number: H01L29/78696 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/1225 ,  H01L27/14634 ,  H01L29/24 ,  H01L29/66818 ,  H01L29/7853 ,  H01L29/7869

Abstract: The present invention provides a transistor having a high on-state current. The transistor includes a plurality of fins, a first oxide semiconductor, a gate insulating film, and a gate electrode. One of adjacent two fins includes a second oxide semiconductor and a third oxide semiconductor. The other includes a fourth oxide semiconductor and the third oxide semiconductor. The second oxide semiconductor and the fourth oxide semiconductor include regions that face each other with the gate electrode positioned therebetween. The gate electrode and the second oxide semiconductor overlap with each other with the gate insulating film and the first oxide semiconductor positioned therebetween. The gate electrode and the fourth oxide semiconductor overlap with each other with the gate insulating film and the first oxide semiconductor positioned therebetween.

Abstract translation: 本发明提供一种具有高导通电流的晶体管。 晶体管包括多个散热片，第一氧化物半导体，栅极绝缘膜和栅电极。 相邻的两个散热片之一包括第二氧化物半导体和第三氧化物半导体。 另一方面包括第四氧化物半导体和第三氧化物半导体。 第二氧化物半导体和第四氧化物半导体包括彼此面对的区域，栅电极位于它们之间。 栅电极和第二氧化物半导体彼此重叠，栅极绝缘膜和第一氧化物半导体位于它们之间。 栅电极和第四氧化物半导体与栅极绝缘膜和位于其间的第一氧化物半导体彼此重叠。

公开(公告)号：WO2015000204A1

公开(公告)日：2015-01-08

申请号：PCT/CN2013/080887

申请日：2013-08-06

Applicant: 中国科学院微电子研究所

Inventor： 殷华湘 ,  马小龙 ,  徐唯佳 ,  徐秋霞 ,  朱慧珑

IPC: H01L21/336

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: 本发明公开了一种FinFET器件及其制造方法，包括：多个鰭片结构，在衬底上沿第一方向延伸；多个栅极堆叠，沿第二方向延伸并且跨越了每个鰭片结构；多个源漏区，位于每个栅极堆叠沿第二方向两侧；多个沟道区，由位于多个源漏区之间的鰭片结构构成；其中，每个鰭片结构沿第二方向的侧壁具有多个突起。依照本发明的FinFET器件及其制作方法，在鰭片侧面形成连续突起特别是弧线表面，提高了抑制短沟道效应的能力，同时在同一平面投影面积下增大了沟道有效导电总截面面积，从而提高了器件总体性能。