公开(公告)号：WO2022055405A1

公开(公告)日：2022-03-17

申请号：PCT/SE2021/050853

申请日：2021-09-07

Applicant: SMOLTEK AB

Inventor： LUNDAHL, Karl

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/538

Abstract: An electronic component package, comprising a package part comprising a plurality of contact pads on a first surface of the package part; a passive component having a first surface including contact pads bonded to a first set of contact pads in the plurality of contact pads on the first surface of the package part, and a second surface spaced apart from the first surface; a plurality of connecting structures for external electrical connection of the electronic component package; and an RDL stack interconnecting a second set of contact pads in the plurality of contact pads on the first surface of the package part with the connecting structures for external electrical connection, the RDL stack comprising: a first conductor layer; a second conductor layer; and a dielectric layer arranged between the first conductor layer and the second conductor layer and comprising vias for conductively connecting the first conductor layer and the second conductor layer.

公开(公告)号：WO2012052051A1

公开(公告)日：2012-04-26

申请号：PCT/EP2010/065654

申请日：2010-10-18

Applicant: SMOLTEK AB ,  KABIR, Mohammad Shafiqul

Inventor： KABIR, Mohammad Shafiqul

IPC: D01F9/127 ,  C01B31/02

CPC classification number: D01F9/127 ,  B05D3/107 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/16 ,  C01B32/162 ,  C01B32/18 ,  C23C16/44 ,  H01L29/0676 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/413 ,  H01L29/775 ,  Y10T428/12396

Abstract: A method for manufacturing a plurality of nanostructures (101) on a substrate (102). The method comprises the steps of: depositing a bottom layer (103) on an upper surface of the substrate (102), the bottom layer (103) comprising grains having a first average grain size; depositing a catalyst layer (104) on an upper surface of the bottom layer (103), the catalyst layer (104) comprising grains having a second average grain size different from the first average grain size, thereby forming a stack of layers comprising the bottom layer (103) and the catalyst layer (104); heating the stack of layers to a temperature where nanostructures (101) can form; and providing a gas comprising a reactant such that the reactant comes into contact with the catalyst layer (104).

Abstract translation: 一种用于在基板（102）上制造多个纳米结构（101）的方法。 该方法包括以下步骤：在衬底（102）的上表面上沉积底层（103），底层（103）包括具有第一平均晶粒尺寸的晶粒; 在所述底层（103）的上表面上沉积催化剂层（104），所述催化剂层（104）包含具有不同于所述第一平均晶粒尺寸的第二平均晶粒尺寸的晶粒，从而形成包括所述底层 层（103）和催化剂层（104）; 将层叠层加热到纳米结构（101）可以形成的温度; 以及提供包含反应物的气体，使得反应物与催化剂层（104）接触。

公开(公告)号：WO2008054283A1

公开(公告)日：2008-05-08

申请号：PCT/SE2007/000951

申请日：2007-10-29

Applicant: SMOLTEK AB ,  KABIR, Mohammad, Shafiqul

Inventor： KABIR, Mohammad, Shafiqul

IPC: G02B6/122 ,  C01B31/02 ,  D01F9/127

CPC classification number: G02B6/1225 ,  B82Y20/00

Abstract: The present invention provides for photonic crystals comprising nanostructures grown on a conducting or insulating substrate, and a method of making the same. The photonic crystals can be used in components such as artificial photonic crystals for photonic devices and circuits.

Abstract translation: 本发明提供了包含在导电或绝缘基板上生长的纳米结构的光子晶体及其制造方法。 光子晶体可用于诸如用于光子器件和电路的人造光子晶体的组件。

公开(公告)号：WO2022194677A1

公开(公告)日：2022-09-22

申请号：PCT/EP2022/056237

申请日：2022-03-10

Applicant: SMOLTEK AB

Inventor： DESMARIS, Vincent ,  WENGER, Fabian

IPC: C25B9/19 ,  C25B15/021

Abstract: An electrolyzer (100) comprising a first (110) and a second (120) electrode and an ion exchange membrane (130) arranged in-between the first and the second electrode. Each electrode comprises an electrically conductive element (111, 121). At least one of the electrodes also comprises a catalyst structure (140) comprising an electrically conductive material. The electrolyzer also comprises at least one feeding means (160, 320, 330, 410), wherein the feeding means (160, 320, 330, 410) is arranged to introduce a variable electromagnetic field into the electrolyzer (100). The variable electromagnetic field is arranged to create a temperature gradient in the electrolyzer (100) by increasing a temperature of the catalyst structure (140).

公开(公告)号：WO2021262067A1

公开(公告)日：2021-12-30

申请号：PCT/SE2021/050582

申请日：2021-06-15

Applicant: SMOLTEK AB

Inventor： KABIR, M Shafiqul ,  DESMARIS, Vincent ,  JOHANSSON, Anders ,  TIVERMAN, Ola ,  LUNDAHL, Karl ,  ANDERSSON, Rickard ,  SALEEM, Muhammad Amin ,  BYLUND, Maria ,  MARKNÄS, Victor

IPC: H01L27/146 ,  H01L21/78 ,  H01L27/14609 ,  H01L27/14634

Abstract: An image sensor comprising an image sensor layer having a plurality of image sensor layer contact pads; and a plurality of photo-sensitive elements, each being coupled to a respective image sensor layer contact pad; and a capacitor layer having: a plurality of first capacitor contact structures, each being constituted by a capacitor layer top contact pad bonded to a respective image sensor layer contact pad of the image sensor layer; a plurality of second capacitor contact structures; and a plurality of capacitors, embedded in a first dielectric material, each capacitor including at least one electrically conductive vertical nanostructure electrically conductively connected to one of a respective first capacitor contact structure and a respective second capacitor contact structure, and conductively separated from the other one of the respective first capacitor contact structure and the respective second capacitor contact structure by a layer of a second dielectric material.

公开(公告)号：WO2021158158A1

公开(公告)日：2021-08-12

申请号：PCT/SE2021/050053

申请日：2021-01-28

Applicant: SMOLTEK AB

Inventor： KABIR, M Shafiqul ,  DESMARIS, Vincent ,  JOHANSSON, Anders ,  TIVERMAN, Ola ,  LUNDAHL, Karl ,  ANDERSSON, Rickard ,  SALEEM, Muhammad Amin ,  BYLUND, Maria ,  MARKNÄS, Victor

IPC: H01L23/522 ,  H01G4/008 ,  H01G4/06 ,  H01L27/02 ,  H05K1/18 ,  B82B1/00 ,  B82Y40/00 ,  H03K19/003

Abstract: An electronic system comprising a substrate with a substrate conductor pattern including substrate pads; a semiconductor component with active circuitry, and component pads coupled to the active circuitry of the semiconductor component and connected to the substrate pads of the substrate; a power source interface for receiving power from a power source; and a power distribution network for distributing power from the power source interface to the active circuitry of the semiconductor component. The power distribution network includes a first capacitor realized by conductive structures comprised in the semiconductor component, the first capacitor being coupled to a first component pad and a second component pad of the semiconductor component; a second capacitor arranged between the substrate and the semiconductor component, the second capacitor being coupled to the first component pad and the second component pad of the component package; and a power grid portion of the substrate conductor pattern.

公开(公告)号：WO2010015333A3

公开(公告)日：2010-05-27

申请号：PCT/EP2009005340

申请日：2009-07-23

Applicant: SMOLTEK AB ,  MUHAMMAD AMIN SALEEM ,  BRUD DAVID ,  BERG JONAS ,  KABIR MOHAMMAD SHALIQUAL ,  DESMARIS VINCENT

Inventor： MUHAMMAD AMIN SALEEM ,  BRUD DAVID ,  BERG JONAS ,  KABIR MOHAMMAD SHALIQUAL ,  DESMARIS VINCENT

IPC: G03F7/00

CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  Y10S977/932

Abstract: Template and method of making high aspect ratio template, stamp, and imprinting at nanoscale using nanostructures for the purpose of lithography, and to the use of the template to create perforations on materials and products.

Abstract translation: 使用纳米结构制备高纵横比模板，印模和压印的模板和方法，用于光刻，以及使用模板在材料和产品上形成穿孔。

公开(公告)号：WO2021211038A1

公开(公告)日：2021-10-21

申请号：PCT/SE2021/050335

申请日：2021-04-13

Applicant: SMOLTEK AB

Inventor： KABIR, M Shafiqul ,  DESMARIS, Vincent ,  JOHANSSON, Anders ,  TIVERMAN, Ola ,  LUNDAHL, Karl ,  ANDERSSON, Rickard ,  SALEEM, Muhammad Amin ,  BYLUND, Maria ,  MARKNÄS, Victor

IPC: H01G4/005 ,  H01G4/06 ,  H01G4/30 ,  H01L27/02 ,  H05K1/18 ,  B82B1/00 ,  B82Y40/00

Abstract: A MIM energy storage device comprising a bottom electrode; a plurality of electrically conductive vertical nanostructures; a bottom conduction- controlling layer conformally coating each nanostructure in the plurality of electrically conductive vertical nanostructures; and a layered stack of alternating conduction-controlling layers and electrode layers conformally coating the bottom conduction-controlling layer, the layered stack including at least a first odd-numbered electrode layer at a bottom of the layered stack, a first odd-numbered conduction-controlling layer directly on the first odd- numbered electrode layer, and a first even-numbered electrode layer directly on the first odd-numbered conduction-controlling layer. Each even-numbered electrode layer in the layered stack is electrically conductively connected to the bottom electrode; and each odd-numbered electrode layer in the layered stack is electrically conductively connected to any other odd-numbered electrode layer in the layered stack.

公开(公告)号：WO2020112005A1

公开(公告)日：2020-06-04

申请号：PCT/SE2019/051176

申请日：2019-11-20

Applicant: SMOLTEK AB

Inventor： KABIR, M Shafiqul ,  DESMARIS, Vincent ,  ANDERSSON, Rickard ,  SALEEM, Muhammad Amin ,  BYLUND, Maria ,  JOHANSSON, Anders ,  LILJEBERG, Fredrik ,  TIVERMAN, Ola

IPC: H01G4/008 ,  H01G4/06 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L27/02 ,  H05K1/18 ,  B82B1/00 ,  B82Y40/00 ,  H01L25/11

Abstract: A semiconductor assembly, comprising: a first semiconductor die including processing circuitry and pads, said first semiconductor die having a first surface and a second surface opposite the first surface; a second semiconductor die including memory circuitry and pads, said second semiconductor die being arranged on one of the first surface and the second surface of said first semiconductor die, and pads of said second semiconductor die being coupled to pads of said first semiconductor die; and at least a first capacitor having terminals, said first capacitor being arranged on one of the first surface and the second surface of said first semiconductor die and the terminals of said capacitor being coupled to pads of said first semiconductor die.

公开(公告)号：WO2010015333A2

公开(公告)日：2010-02-11

申请号：PCT/EP2009/005340

申请日：2009-07-23

Applicant: SMOLTEK AB ,  MUHAMMAD, Amin Saleem ,  BRUD, David ,  BERG, Jonas ,  KABIR, Mohammad, Shaliqual ,  DESMARIS, Vincent

Inventor： MUHAMMAD, Amin Saleem ,  BRUD, David ,  BERG, Jonas ,  KABIR, Mohammad, Shaliqual ,  DESMARIS, Vincent

IPC: G03F7/00

CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  Y10S977/932

Abstract: Template and method of making high aspect ratio template, stamp, and imprinting at nanoscale using nanostructures for the purpose of lithography, and to the use of the template to create perforations on materials and products.

Abstract translation: 使用纳米结构制备高纵横比模板，印模和压印的模板和方法，用于光刻，以及使用模板在材料和产品上形成穿孔。