公开(公告)号：WO2007002868A1

公开(公告)日：2007-01-04

申请号：PCT/US2006/025469

申请日：2006-06-28

Applicant: INTEL CORPORATION ,  NICKERSON, Robert ,  TAGGART, Brian ,  SPREITZER, Ronald

Inventor： NICKERSON, Robert ,  TAGGART, Brian ,  SPREITZER, Ronald

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4917 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Logic and memory may be packaged together in a single integrated circuit package that, in some embodiments, has high input/output pin count and low stack height. In some embodiments, the logic may be stacked on top of the memory which may be stacked on a flex substrate. Such a substrate may accommodate a multilayer interconnection system which facilitates high pin count and low package height. In some embodiments, the package may be wired so that the memory may only be accessed through the logic.

Abstract translation: 逻辑和存储器可以一起封装在单个集成电路封装中，在一些实施例中，其具有高输入/输出引脚数和低堆栈高度。 在一些实施例中，逻辑可以堆叠在可以堆叠在柔性基板上的存储器的顶部上。 这样的基板可以容纳有助于高引脚数和低封装高度的多层互连系统。 在一些实施例中，封装可以被布线，使得只能通过逻辑访问存储器。