公开(公告)号：WO2011068025A1

公开(公告)日：2011-06-09

申请号：PCT/JP2010/070248

申请日：2010-11-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  TAKAHASHI, Kei ,  ITO, Yoshiaki ,  INOUE, Hiroki ,  NISHIJIMA, Tatsuji

Inventor： TAKAHASHI, Kei ,  ITO, Yoshiaki ,  INOUE, Hiroki ,  NISHIJIMA, Tatsuji

IPC: H02M3/155 ,  H01L29/786

CPC classification number: H02M3/156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869 ,  H02M3/155

Abstract: A DC converter circuit having high reliability is provided. The DC converter circuit includes: an inductor configured to generate electromotive force in accordance with a change in flowing current; a transistor including a gate, a source, and a drain, which is configured to control generation of the electromotive force in the inductor by being on or off; a rectifier in a conducting state when the transistor is off; and a control circuit configured to control on and off of the transistor. The transistor includes an oxide semiconductor layer whose hydrogen concentration is less than or equal to 5 x 10 19 atoms/cm 3 as a channel formation layer.

Abstract translation: 提供了具有高可靠性的DC转换器电路。 DC转换器电路包括：电感器，被配置为根据流动电流的变化产生电动势; 包括栅极，源极和漏极的晶体管，其被配置为通过导通或关断来控制电感器中的电动势的产生; 当晶体管截止时处于导通状态的整流器; 以及被配置为控制晶体管的导通和截止的控制电路。 晶体管包括作为沟道形成层的氢浓度小于或等于5×1019原子/ cm3的氧化物半导体层。

公开(公告)号：WO2011145706A1

公开(公告)日：2011-11-24

申请号：PCT/JP2011/061593

申请日：2011-05-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  TAKAHASHI, Kei ,  ITO, Yoshiaki

Inventor： TAKAHASHI, Kei ,  ITO, Yoshiaki

IPC: H02M3/155

CPC classification number: H02M3/156 ,  H02M2001/0003

Abstract: An object is to reduce power consumption of a semiconductor device including a DC-DC converter circuit. The semiconductor device includes a DC-DC converter circuit and a microprocessor. The DC-DC converter circuit includes a conversion circuit including an inductor and a transistor, and a control circuit including a comparison circuit and a logic circuit. A hysteresis comparator is used as the comparison circuit. In the control circuit, the comparison circuit compares an output signal of the conversion circuit with a first reference potential or a second reference potential, and the logic circuit performs arithmetic operation between an output signal of the comparison circuit and a clock signal of the microprocessor. In the conversion circuit, the transistor controls current flowing through the inductor in accordance with an output signal of the logic circuit, and the output signal of the conversion circuit is generated in accordance with the current flowing through the inductor.

Abstract translation: 目的是降低包括DC-DC转换器电路的半导体器件的功耗。 半导体器件包括DC-DC转换器电路和微处理器。 DC-DC转换器电路包括具有电感和晶体管的转换电路，以及包括比较电路和逻辑电路的控制电路。 使用滞后比较器作为比较电路。 在控制电路中，比较电路将转换电路的输出信号与第一参考电位或第二参考电位进行比较，逻辑电路在比较电路的输出信号和微处理器的时钟信号之间进行运算。 在转换电路中，晶体管根据逻辑电路的输出信号控制流过电感器的电流，并且根据流过电感器的电流产生转换电路的输出信号。

公开(公告)号：WO2011058885A1

公开(公告)日：2011-05-19

申请号：PCT/JP2010/069226

申请日：2010-10-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  TAKAHASHI, Kei ,  YAMAZAKI, Shunpei

Inventor： TAKAHASHI, Kei ,  YAMAZAKI, Shunpei

IPC: G09F9/30 ,  G09G3/20 ,  G09G3/30 ,  H01L27/32 ,  H01L29/786 ,  H01L51/50

CPC classification number: H01L27/1225 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2300/0814 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/78672 ,  H01L29/7869

Abstract: A display device includes a pixel portion including a plurality of pixels each including a first transistor, a second transistor, and a light-emitting element, in which a gate of the first transistor is electrically connected to a scan line, one of a source and a drain of the first transistor is electrically connected to a signal line, and the other of them is electrically connected to a gate of the second transistor; one of a source and a drain of the second transistor is electrically connected to a power supply line and the other of them is electrically connected to the light-emitting element, and the first transistor includes an oxide semiconductor layer. A period when the display device displays a still image includes a period in which output of a signal to all the scan lines in the pixel portion is stopped.

Abstract translation: 显示装置包括像素部分，其包括多个像素，每个像素包括第一晶体管，第二晶体管和发光元件，其中第一晶体管的栅极电连接到扫描线，源和源之一 第一晶体管的漏极与信号线电连接，另一端与第二晶体管的栅极电连接; 第二晶体管的源极和漏极之一电连接到电源线，并且另一个电连接到发光元件，并且第一晶体管包括氧化物半导体层。 显示装置显示静止图像的周期包括对像素部分中的所有扫描线的信号的输出停止的时段。

公开(公告)号：WO2011052366A1

公开(公告)日：2011-05-05

申请号：PCT/JP2010/067809

申请日：2010-10-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  YAMAZAKI, Shunpei ,  KOYAMA, Jun ,  TAKAHASHI, Kei ,  TSUBUKU, Masashi ,  NODA, Kosei

Inventor： YAMAZAKI, Shunpei ,  KOYAMA, Jun ,  TAKAHASHI, Kei ,  TSUBUKU, Masashi ,  NODA, Kosei

IPC: H02M3/07 ,  H01L21/822 ,  H01L27/04 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H02M3/07 ,  H02M3/158

Abstract: A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/ μm. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.

Abstract translation: 电压调节器电路包括晶体管和电容器。 晶体管包括栅极，源极和漏极，第一信号被输入到源极和漏极中的一个，作为时钟信号的第二信号被输入到栅极，氧化物半导体层被用于沟道 形成层，截止电流小于或等于10AA /μm。 电容器包括第一电极和第二电极，第一电极电连接到晶体管的源极和漏极中的另一个，并且高电源电压和低电源电压交替施加到第二电极。

公开(公告)号：WO2009090969A1

公开(公告)日：2009-07-23

申请号：PCT/JP2009/050404

申请日：2009-01-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  FUKUMOTO, Ryota ,  MIYAKE, Hiroyuki ,  TANADA, Yoshifumi ,  TAKAHASHI, Kei

Inventor： FUKUMOTO, Ryota ,  MIYAKE, Hiroyuki ,  TANADA, Yoshifumi ,  TAKAHASHI, Kei

IPC: G09G3/30 ,  G09G3/20 ,  H01L51/50

CPC classification number: G09G3/3225 ,  G09G2300/043 ,  G09G2300/0866 ,  G09G2320/0223 ,  G09G2330/025

Abstract: The amplitude of a potential of a signal line is decreased and a scan line driver circuit is prevented from being excessively loaded. A light-emitting device includes a light-emitting element; a first power supply line having a first potential; a second power supply line having a second potential; a first transistor for controlling a connection between the first power supply line and the light-emitting element; a second transistor, which is controlled in accordance with a video signal, whether outputting the second potential applied from the second power supply line or not; a switching element for selecting either the first potential applied from the first power supply line or the output of the second transistor; and a third transistor for selecting whether the first potential or the output of the second transistor which is selected by the switch is applied to a gate of the first transistor.

Abstract translation: 信号线的电位的幅度减小，防止扫描线驱动电路过载。 发光装置包括发光元件; 具有第一电位的第一电源线; 具有第二电位的第二电源线; 用于控制第一电源线和发光元件之间的连接的第一晶体管; 根据视频信号控制的第二晶体管，是否输出从第二电源线施加的第二电位; 用于选择从第一电源线施加的第一电位或第二晶体管的输出的开关元件; 以及第三晶体管，用于选择由开关选择的第二晶体管的第一电位或输出是施加到第一晶体管的栅极。

公开(公告)号：WO2010038602A1

公开(公告)日：2010-04-08

申请号：PCT/JP2009/065980

申请日：2009-09-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  INOUE, Hiroki ,  TAKAHASHI, Kei

Inventor： INOUE, Hiroki ,  TAKAHASHI, Kei

IPC: G06K19/07 ,  G05F1/10 ,  G05F1/56 ,  G05F3/24

CPC classification number: G05F3/24 ,  G06K19/0701 ,  G06K19/07749

Abstract: A semiconductor device monitors a voltage between a reference potential and an input potential and obtains a constant output potential regardless of a value of the voltage, after the voltage exceeds a predetermined threshold voltage in such a manner that the semiconductor device divides a voltage between the reference potential and the input potential using a plurality of first non-linear elements and at least one linear element to constantly generate a first bias voltage regardless of a value of the voltage, divides a voltage between the reference potential and the input potential using a plurality of second non-linear elements with reference to the first bias voltage to constantly generate a second bias voltage regardless of a value of the voltage, and determines the output potential with reference to the second bias voltage.

Abstract translation: 半导体器件监视参考电位和输入电位之间的电压，并且在电压超过预定阈值电压之后，获得恒定的输出电位，而不管电压值如何，使得半导体器件将参考电压 使用多个第一非线性元件和至少一个线性元件的电位和输入电位以恒定地产生第一偏置电压而不管电压的值，使用多个第一非线性元件和多个线性元件分别在参考电位和输入电位之间分压 参考第一偏置电压的第二非线性元件，以恒定地产生第二偏置电压，而不管电压的值，并且参考第二偏置电压确定输出电位。

公开(公告)号：WO2011155295A1

公开(公告)日：2011-12-15

申请号：PCT/JP2011/061464

申请日：2011-05-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  TAKAHASHI, Kei ,  KOYAMA, Jun ,  ISHII, Masato

Inventor： TAKAHASHI, Kei ,  KOYAMA, Jun ,  ISHII, Masato

IPC: H02M3/155 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/786

CPC classification number: H02M3/156 ,  H01L27/1225 ,  H01L27/1251 ,  H02M3/155 ,  Y02B70/1483

Abstract: Provided is a DC-DC converter with improved power conversion efficiency. A transistor which is incorporated in the DC-DC converter and functions as a switching element for controlling output power includes, in its channel formation region, a semiconductor material having a wide band gap and significantly small off current compared with silicon. The transistor further comprises a back gate electrode, in addition to a general gate electrode, and a back gate control circuit for controlling a potential applied to the back gate electrode in accordance with the output power from the DC-DC converter. The control of the potential applied to the back gate electrode by the back gate control circuit enables the threshold voltage to decrease the on-state resistance when the output power is high and to increase the off-state current when the output power is low.

Abstract translation: 提供了具有改善的功率转换效率的DC-DC转换器。 结合在DC-DC转换器中并用作用于控制输出功率的开关元件的晶体管在其沟道形成区域中包括与硅相比具有宽带隙和显着小的截止电流的半导体材料。 该晶体管还包括除普通栅电极之外的背栅电极和用于根据来自DC-DC转换器的输出功率来控制施加到背栅极的电位的背栅控制电路。 通过背栅极控制电路控制施加到背栅电极的电位，能够在输出功率较高时使阈值电压降低导通电阻，并且在输出功率低时增加关断电流。

公开(公告)号：WO2011145707A1

公开(公告)日：2011-11-24

申请号：PCT/JP2011/061594

申请日：2011-05-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  TAKAHASHI, Kei ,  ITO, Yoshiaki

Inventor： TAKAHASHI, Kei ,  ITO, Yoshiaki

IPC: H02M3/155

CPC classification number: H02M3/158 ,  H02M3/157 ,  H02M2001/0048 ,  Y02B70/1491

Abstract: An object is to reduce power consumption of a semiconductor device including a DC-DC converter circuit. The semiconductor device includes a DC-DC converter circuit and a microprocessor. The DC-DC converter circuit includes a conversion circuit including an inductor and a transistor, and a control circuit including a comparison circuit and a logic circuit. In the control circuit, the comparison circuit compares an output of the conversion circuit and a reference value, and the logic circuit performs an arithmetic operation between an output of the comparison circuit and a clock signal of the microprocessor. In the conversion circuit, the transistor controls a current flowing through the inductor in accordance with an output of the logic circuit, and the output of the conversion circuit is generated in accordance with the current flowing through the inductor.

Abstract translation: 目的是降低包括DC-DC转换器电路的半导体器件的功耗。 半导体器件包括DC-DC转换器电路和微处理器。 DC-DC转换器电路包括具有电感和晶体管的转换电路，以及包括比较电路和逻辑电路的控制电路。 在控制电路中，比较电路将转换电路的输出与参考值进行比较，逻辑电路在比较电路的输出与微处理器的时钟信号之间进行运算。 在转换电路中，晶体管根据逻辑电路的输出控制流过电感器的电流，并且根据流过电感器的电流产生转换电路的输出。

公开(公告)号：WO2011046048A1

公开(公告)日：2011-04-21

申请号：PCT/JP2010/067495

申请日：2010-09-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  YAMAZAKI, Shunpei ,  KOYAMA, Jun ,  MIYAKE, Hiroyuki ,  TAKAHASHI, Kei ,  TOYOTAKA, Kouhei ,  TSUBUKU, Masashi ,  NODA, Kosei ,  KUWABARA, Hideaki

Inventor： YAMAZAKI, Shunpei ,  KOYAMA, Jun ,  MIYAKE, Hiroyuki ,  TAKAHASHI, Kei ,  TOYOTAKA, Kouhei ,  TSUBUKU, Masashi ,  NODA, Kosei ,  KUWABARA, Hideaki

IPC: H01L29/786 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L29/26 ,  G06K19/07758 ,  G11C7/00 ,  G11C19/28 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/0883 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78609 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2223/6677 ,  H02M3/07

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

Abstract translation: 目的是减少用于LSI，CPU或存储器的晶体管的泄漏电流和寄生电容。 使用薄膜晶体管制造诸如LSI，CPU或存储器的半导体集成电路，其中使用氧化物半导体形成沟道形成区域，该氧化物半导体通过去除作为电子给体的杂质而成为本征或本质上的半导体 （供体），并且具有比硅半导体更大的能隙。 通过使用具有充分降低的氢浓度的高度净化的氧化物半导体层的薄膜晶体管，可以实现由于漏电流而具有低功耗的半导体器件。

公开(公告)号：WO2011125566A1

公开(公告)日：2011-10-13

申请号：PCT/JP2011/057496

申请日：2011-03-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  TAKAHASHI, Kei ,  ITO, Yoshiaki

Inventor： TAKAHASHI, Kei ,  ITO, Yoshiaki

IPC: H03K3/356 ,  H03K19/0175 ,  H03K23/00 ,  H03K23/54

CPC classification number: H03K23/54 ,  G06F1/06 ,  H03K21/12 ,  H03K21/406

Abstract: A divider circuit includes a shift register which generates 2 X ( X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal output circuit which generates a signal to be a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2 X pulse signals and outputs it. The divided signal output circuit includes X first transistors which control whether voltage of the signal to be the third clock signal is set to first voltage; and X second transistors which control whether voltage of the signal to be the third clock signal is set to second voltage.

Abstract translation: 分频电路包括根据第一时钟信号或第二时钟信号产生2X（X为大于或等于2的自然数）脉冲信号的移位寄存器，并输出它们;以及分频信号输出电路， 根据2X脉冲信号，信号成为第三时钟信号，其周期比第一时钟信号的周期长十倍，并将其输出。 分频信号输出电路包括：X个第一晶体管，其控制作为第三时钟信号的信号的电压是否被设置为第一电压; 以及X第二晶体管，其控制作为第三时钟信号的信号的电压是否被设定为第二电压。