公开(公告)号：WO2005062190A1

公开(公告)日：2005-07-07

申请号：PCT/US2004/039236

申请日：2004-11-24

Applicant: INTEL CORPORATION ,  BLACK, Bryan ,  SAMRA, Nicholas ,  WEBB, M., Clair

Inventor： BLACK, Bryan ,  SAMRA, Nicholas ,  WEBB, M., Clair

IPC: G06F15/78

CPC classification number: G06F15/7832 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/14 ,  Y02D10/12 ,  Y02D10/13 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.

Abstract translation: 公开了一种多芯片处理器装置和系统。 执行一个或多个指令的处理器逻辑在两个或多个面对面堆叠的骰子之间分配。 处理器包括在堆叠的骰子之间的导电接口，以便于管芯到管芯的通信。

公开(公告)号：WO2015195084A1

公开(公告)日：2015-12-23

申请号：PCT/US2014/042577

申请日：2014-06-16

Applicant: INTEL CORPORATION ,  NELSON, Donald W. ,  WEBB, M Clair ,  MORROW, Patrick ,  JUN, Kimin

Inventor： NELSON, Donald W. ,  WEBB, M Clair ,  MORROW, Patrick ,  JUN, Kimin

IPC: H01L21/335 ,  H01L29/78

CPC classification number: H01L43/02 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0694 ,  H01L27/101 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2224/03 ,  H01L2924/014

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein.

Abstract translation: 一种方法，包括在包括多个电路装置的集成电路装置层的相对侧上形成多个第一互连和多个第二互连，其中形成多个第一互连中的一个和多个第二互连包括嵌入存储器件 在其中。 一种装置，包括在包括多个电路装置的集成电路装置层的相对侧上包括多个第一互连和多个第二互连的基板，其中多个第一互连和多个第二互连中的一个包括存储装置 嵌入其中。