公开(公告)号：WO2011097021A3

公开(公告)日：2014-03-27

申请号：PCT/US2011000197

申请日：2011-02-03

Applicant: MAGIC TECHNOLOGIES INC ,  YANG HSU KAI

Inventor： YANG HSU KAI

IPC: G11C11/00

CPC classification number: G11C7/02 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect.

Abstract translation: 一组SMT MRAM单元具有一个读取参考电路，该参考电流是通过编程具有最大电阻的参考SMT MRAM单元的最小电流和通过最小电阻编程的参考SMT MRAM单元的最大电流之和的总和 。 参考电流在读出放大器的参考输入处形成平均参考电压，用于从阵列的所选SMT MRAM单元读取数据状态，使得参考SMT MRAM单元在读取操作期间不被干扰。 读取参考电路补偿由二阶非匹配效应引起的参考电流中的电流失配。

公开(公告)号：WO2011022029A1

公开(公告)日：2011-02-24

申请号：PCT/US2010/001896

申请日：2010-07-02

Applicant: MAGIC TECHNOLOGIES INC ,  YANG, Hsu, Kai

Inventor： YANG, Hsu, Kai

IPC: G11C11/06

CPC classification number: G11C11/1697 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002

Abstract: This invention describes a circuit and method to write information into individual memory cells while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array During the write operation the voltage is raised for the word line of only one row of the array The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row

Abstract translation: 本发明描述了一种将信息写入各个存储单元的电路和方法，同时最小化其中没有信息被写入的存储单元的单元晶体管中的栅极电压应力。本发明的电路具有用于每个 存储器阵列的行和用于存储器阵列的每个位线的可单独控制的电压源在写入操作期间，对于阵列的仅一行的字线升高电压。然后调整位线电压，使得1为 写入该行中所需的单元格，并将0写入该行中所需的单元格

公开(公告)号：WO2006113093A3

公开(公告)日：2007-01-11

申请号：PCT/US2006011963

申请日：2006-03-30

Applicant: HEADWAY TECHNOLOGIES INC ,  APPLIED SPINTRONICS INC ,  WANG PO-KANG ,  RONG YIN ,  YANG HSU KAI ,  SHI XIZENG

Inventor： WANG PO-KANG ,  RONG YIN ,  YANG HSU KAI ,  SHI XIZENG

IPC: G11C11/00

CPC classification number: G11C8/08 ,  G11C11/15

Abstract: The word line segment select transistor (15) of a segmented word line array (11, 12) is placed on the word line current source side (14). This eliminates many undesirable effects effects currently associated with segmented word line MRAM arrays (18).

Abstract translation: 分割字线阵列（11,12）的字线选择晶体管（15）被放置在字线电流源侧（14）上。 这消除了当前与分段字线MRAM阵列（18）相关联的许多不期望的效果效果。

公开(公告)号：WO2010151297A1

公开(公告)日：2010-12-29

申请号：PCT/US2010/001728

申请日：2010-06-16

Applicant: MAGIC TECHNOLOGIES, INC. ,  YANG, Hsu, Kai

Inventor： YANG, Hsu, Kai

IPC: G06F11/00

CPC classification number: G06F11/106 ,  G06F11/1096 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/46

Abstract: A data scrubbing apparatus corrects disturb data errors occurring in an array of memory cells such as SMT MRAM cells. The data scrubbing apparatus receives an error indication that an error has occurred during a read operation of a grouping of memory cells within the array of memory cells. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data. Based on a scrub threshold value, the data scrubbing apparatus writes the corrected data back after a specific number of errors. The data scrubbing apparatus may further suspend writing back during a writing of data. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

Abstract translation: 数据擦除装置校正在诸如SMT MRAM单元的存储单元阵列中发生的干扰数据错误。 数据擦除装置接收在存储器单元阵列内的一组存储器单元的读取操作期间发生错误的错误指示。 数据擦除装置可以生成描述要擦除的存储器单元的位置的地址。 然后，数据擦除装置命令存储器单元阵列回写校正的数据。 基于擦除阈值，数据擦除装置在经过特定数量的错误之后写入校正后的数据。 数据擦除装置可以在写入数据期间进一步中止写回。 在校正数据的回写期间，数据擦除装置在外部提供忙指示符。

公开(公告)号：WO2010059177A1

公开(公告)日：2010-05-27

申请号：PCT/US2009/005679

申请日：2009-10-19

Applicant: MAGIC TECHNOLOGIES, INC. ,  YANG, Hsu, Kai

Inventor： YANG, Hsu, Kai

IPC: G11C11/14 ,  H01S4/00

CPC classification number: G11C11/1697 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  Y10T29/49002

Abstract: A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical "1 " to the MTJ element of a selected spin-torque MRAM cell.

Abstract translation: 栅极升压电路为自旋转矩MRAM单元的选择开关MOS晶体管的栅极提供升压，以防止通过自旋转矩MRAM单元的MTJ器件的编程电流减小。 自旋转矩MRAM单元阵列由包括MTJ元件和选择开关器件的自旋转矩MRAM单元组成。 本地字线与多个自旋扭矩MRAM单元的一行相关联，并且连接到MRAM单元行的选择开关器件的栅极端子以控制激活和去激活。 一个栅极升压电路放置在相关联的全局字线和相关的本地字线之间。 栅极升压电路在将逻辑“1”写入所选择的自旋转矩MRAM单元的MTJ元件时，提高所选择的开关器件的栅极的电压。

公开(公告)号：WO2006113093A2

公开(公告)日：2006-10-26

申请号：PCT/US2006/011963

申请日：2006-03-30

Applicant: HEADWAY TECHNOLOGIES, INC. ,  APPLIED SPINTRONICS, INC. ,  WANG, Po-Kang ,  RONG, Yin ,  YANG, Hsu, Kai ,  SHI, Xizeng

Inventor： WANG, Po-Kang ,  RONG, Yin ,  YANG, Hsu, Kai ,  SHI, Xizeng

IPC: G11C11/00

CPC classification number: G11C8/08 ,  G11C11/15

Abstract: The word line segment select transistor of a segmented word line array is placed on the word line current source side. This eliminates many undesirable effects currently associated with segmented word line MRAM arrays.

Abstract translation: 分段字线阵列的字线选择晶体管被放置在字线电流源侧。 这消除了目前与分段字线MRAM阵列相关联的许多不期望的影响。

公开(公告)号：WO2006104876A2

公开(公告)日：2006-10-05

申请号：PCT/US2006/010752

申请日：2006-03-24

Applicant: HEADWAY TECHNOLOGIES, INC. ,  APPLIED SPINTRONICS, INC. ,  YANG, Hsu, Kai ,  WANG, Po-kang ,  SHI, Xizeng

Inventor： YANG, Hsu, Kai ,  WANG, Po-kang ,  SHI, Xizeng

IPC: G11C11/00

CPC classification number: G11C8/14 ,  G11C11/15

Abstract: In an MRAM array based on MTJs, the size of segmented word line select transistors and their associated connections become a significant overhead, espe¬ cially when the operating point is chosen deep along the hard axis of the asteroid curve. This problem has been overcome by placing the big segmented word line select transistors under the MTJ array and reducing the overall MRAM cell array down to a level comparable to a simple Cross Point MRAM array.

Abstract translation: 在基于MTJ的MRAM阵列中，分段字线选择晶体管及其相关连接的大小成为显着的开销，特别是当沿着小行星曲线的硬轴选择工作点时。 通过将大分段字线选择晶体管放置在MTJ阵列下并将整个MRAM单元阵列降低到与简单的交叉点MRAM阵列相当的水平，已经克服了这个问题。

公开(公告)号：WO2010138160A1

公开(公告)日：2010-12-02

申请号：PCT/US2010/001453

申请日：2010-05-17

Applicant: MAGLC TECHNOLOGIES, INC. ,  WANG, PoKang ,  YANG, Hsu Kai

Inventor： WANG, PoKang ,  YANG, Hsu Kai

IPC: G11C11/00

CPC classification number: G11C7/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: We describe a reference cell structure for determining data storing cell resistances in an SMT (spin moment transfer) MTJ (magnetic tunneling junction) MRAM array by comparing data cell currents with those of the reference cell. Since the reference cell also utilizes spin moment transfer (SMT) magnetic tunneling junction (MTJ) cells, there would ordinarily be the danger that the act of reading the reference cell could change its magnetization orientations and be a source of error for subsequent comparisons. Therefore the present invention describes a new circuit arrangement for the reference cell that directs read currents through two SMT MTJ cells in opposite directions so that the transfer of spin moments cannot affect the relative magnetization directions of the cells.

Abstract translation: 我们描述了通过将数据单元电流与参考单元电流进行比较来确定在SMT（自旋矩转移）MTJ（磁隧道结）MRAM阵列中存储单元电阻的数据的参考单元结构。 由于参考单元还利用自旋力矩传递（SMT）磁隧道结（MTJ）单元，因此读取参考单元的行为通常会改变其磁化方向，并作为后续比较的误差源。 因此，本发明描述了用于参考单元的新电路装置，其引导读取电流通过两个SMT MTJ单元在相反方向上，使得自旋转矩的转移不会影响单元的相对磁化方向。

公开(公告)号：WO2010129040A1

公开(公告)日：2010-11-11

申请号：PCT/US2010/001312

申请日：2010-05-04

Applicant: MAGIC TECHNOLOGIES, INC. ,  YANG, Hsu Kai

Inventor： YANG, Hsu Kai

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1675 ,  Y10T29/41

Abstract: An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal. Out-of-phase switching devices are connected to the source lines for selectively transferring the out-of-phase signal to the at least one source lines. Column select transistors are connected to the single bit lines for transferring an in-phase data signal to a selected column of the SMT MRAM cells. A precharge circuit selectively charges or discharges the single bit lines. Ground switching devices selectively connect to the source lines to a ground reference voltage source. A method for programming a selected SMT MRAM cell within a provided SMT MRAM device is described.

Abstract translation: SMT MRAM器件包括以行和列阵列排列的多个SMT MRAM单元。 单位线连接SMT MRAM单元的列，用于接收同相数据信号。 源极线连接SMT MRAM单元的行对，用于接收异相数据信号。 异相开关器件连接到源极线，用于选择性地将异相信号传输到至少一个源极线。 列选择晶体管连接到单位线，用于将同相数据信号传送到SMT MRAM单元的选定列。 预充电电路选择性地对单个位线进行充电或放电。 接地开关器件选择性地将源极线连接到接地参考电压源。 描述了在所提供的SMT MRAM设备内对所选择的SMT MRAM单元进行编程的方法。

公开(公告)号：WO2005124558A3

公开(公告)日：2008-08-21

申请号：PCT/US2005020302

申请日：2005-06-09

Applicant: HEADWAY TECHNOLOGIES INC ,  YANG HSU KAI KARL ,  SHI XIZENG ,  WANG PO-KANG ,  YANG BRUCE YEE

Inventor： YANG HSU KAI KARL ,  SHI XIZENG ,  WANG PO-KANG ,  YANG BRUCE YEE

IPC: G11C11/00 ,  G06F12/00 ,  G11C8/14 ,  G11C11/14 ,  G11C11/15

CPC classification number: G11C11/15 ,  G11C8/14

Abstract: A method and system for programming and reading a magnetic memory is disclosed. The magnetic memory includes a plurality of selectable word line segments and a plurality of magnetic storage cells corresponding to each word line segment. The method and system include reading the magnetic storage cells corresponding to a word line segment to determine a state of each magnetic storage cell. In one aspect, the method and system also include utilizing at least one storage for storing a state of each of the magnetic storage cells determined during a read operation made during a write operation. The method and system also include writing data to a portion of the magnetic cells corresponding to the word line segment after the reading. The method and system also include rewriting the state to each of a remaining portion of the magnetic storage cells corresponding to the word line segment at substantially the same time as the portion of the magnetic cells are written.

Abstract translation: 公开了一种用于编程和读取磁存储器的方法和系统。 磁存储器包括多个可选字线段和对应于每个字线段的多个磁存储单元。 该方法和系统包括读取对应于字线段的磁存储单元以确定每个磁存储单元的状态。 一方面，该方法和系统还包括利用至少一个存储器来存储在写入操作期间进行的读取操作期间确定的每个磁存储单元的状态。 该方法和系统还包括在读取之后将数据写入对应于字线段的磁性单元的一部分。 所述方法和系统还包括将所述状态重写为与写入所述磁性单元的所述部分基本相同的时间对应于所述字线段的所述磁存储单元的剩余部分。