公开(公告)号：WO2006020357A1

公开(公告)日：2006-02-23

申请号：PCT/US2005/026205

申请日：2005-07-25

申请人： ATMEL CORPORATION

发明人： SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

IPC分类号： G11C16/04

CPC分类号： G11C17/18 ,  G11C16/20 ,  G11C2216/30

摘要： Fuse data used to configure ancillary circuits (81) used with a non-volatile serial memory core (51) are stored in locations (54) within the memory core. As a first opcode or word is sent on a serial bus (61) to the memory, a logic circuit (67, 75, 77) intercepts the word and generates read fuse enable pulses that fetch the fuse data and configure the ancillary circuits before the last bit of the first command byte arrives. If a read operation is designated, the memory circuits are configured to read. If a write operation is designated, further fuse data is fetched from the memory core to configure ancillary circuits for writing. The fuse data is written to the memory core at the time of circuit manufacture thereby obviating the need for separate storage locations.

摘要翻译： 用于配置与非易失性串行存储器核心（51）一起使用的辅助电路（81）的保险丝数据被存储在存储器核心内的位置（54）中。 当串行总线（61）上的第一个操作码或字被发送到存储器时，逻辑电路（67,75,77）拦截该字并产生读保险丝使能脉冲，其获取保险丝数据并在辅助电路之前配置 第一个命令字节的最后一位到达。 如果指定了读取操作，则存储器电路被配置为读取。 如果指定写入操作，则从存储器核心获取进一步的熔丝数据以配置用于写入的辅助电路。 在电路制造时，熔丝数据被写入存储器核心，从而避免了对单独的存储位置的需要。

公开(公告)号：WO2007124304A2

公开(公告)日：2007-11-01

申请号：PCT/US2007/066779

申请日：2007-04-17

申请人： ATMEL CORPORATION ,  NG, Philip, S. ,  SON, Jinshu

发明人： NG, Philip, S. ,  SON, Jinshu

IPC分类号： H03K19/003

CPC分类号： H03K19/01721 ,  H03K19/01742

摘要： A dual -wire communications bus circuit (300), compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit (300) to couple to a communications bus (317). The bus (317) has a first line for carrying data signals from a master device (201) to one or more slave devices (315A- 315H) and a second line to carry a clock signal between the devices (315A-315H). A pullup resistor (305, 311) is located in each part of the communications bus circuit (300); the pullup resistor (305) in the first part couples to the first line of the communications bus (317) and the pullup resistor (311) in the second part couples to the second line of the communications bus (317). To improve data throughput and reduce noise, an active pullup device (301A2-301H2), working in conjunction with the pullup resistor (311), is located in each part of the communications bus circuit (300), providing a high logic level on at least one of the communications bus lines.

摘要翻译： 与现有的双线总线协议兼容的双线通信总线电路（300）包括通信总线电路（300）的第一和第二部分，以耦合到通信总线（317）。 总线（317）具有用于将数据信号从主设备（201）传送到一个或多个从设备（315A-315H）的第一线路和用于在设备（315A-315H）之间传送时钟信号）的第二线路。 上拉电阻（305,311）位于通信总线电路（300）的每个部分中; 第一部分中的上拉电阻（305）耦合到通信总线（317）的第一行，并且第二部分中的上拉电阻（311）耦合到通信总线（317）的第二行。 为了提高数据吞吐量并降低噪声，与通信总线电路（300）的每个部分中位于与上拉电阻器（311）一起工作的有源上拉器件（301A2-301H2），提供高逻辑电平 至少有一条通信总线。

公开(公告)号：WO2005043589A2

公开(公告)日：2005-05-12

申请号：PCT/US2004/033962

申请日：2004-10-13

申请人： ATMEL CORPORATION

发明人： CHAN, Johnny ,  NG, Philip, S. ,  WONG, Tinwai

IPC分类号： H01L

CPC分类号： G11C16/349

摘要： An integrated circuit device (10) includes a plurality of non-volatile memory cells (V1 and V2) associated with a plurality of flag cells (F1 and F2) storing managing data. The managing data of the flag cells (F1 and F2) forms a data set. The data set is utilized to determine to which memory cell of the plurality of memory cells (V1 and V2) to write new data and from which of the memory cells (V1 and V2) to read currently stored data. The data set is changed to a different data set whenever a new value is written to a designated memory cell to indicate an alternate memory cell to be written to next and an alternate memory cell to be read from next. The data set may be changed by alternately writing a new value to a different flag cell in each successive change of the data set.

摘要翻译： 集成电路装置（10）包括与存储管理数据的多个标志单元（F1和F2）相关联的多个非易失性存储单元（V1和V2）。 标志单元（F1和F2）的管理数据形成数据集。 数据组用于确定多个存储单元（V1和V2）中的哪个存储单元写入新数据以及从哪个存储器单元（V1和V2）读取当前存储的数据。 每当将新值写入指定的存储器单元以指示要写入下一个的备用存储器单元和从下一个要读取的备用存储器单元时，数据集将被改变为不同的数据组。 可以通过在数据集的每个连续变化中交替地将新值写入不同的标志单元来改变数据集。

公开(公告)号：WO2008150420A1

公开(公告)日：2008-12-11

申请号：PCT/US2008/006795

申请日：2008-05-29

申请人： ATMEL CORPORATION ,  NG, Philip, S. ,  YE, Ken

发明人： NG, Philip, S. ,  YE, Ken

IPC分类号： G08B23/00

CPC分类号： H04L12/40045 ,  H04L12/40032 ,  H04L2012/40273

摘要： Embodiments disclosed are apparatus comprising a processing circuit having signal and power input ports to couple to a single-wire interface providing electncal communication of both signals and power at a power supply voltage level Also provided Is a charging transistor coupled at a first source/dram terminal to the single-wire interface Further provided is a charge storage device coupled to the second source/drain terminal of the transistor at a connection point and to the power input port of the processing circuit at said connection point There is also a control device having an input coupled to the single-wire interface, a control output coupled to the gate of the transistor, and powered by the charge storage device at the connection point, such that the transistor charges the storage device when the single-wire interface voltage is at a power supply voltage level.

摘要翻译： 所公开的实施例包括具有信号和功率输入端口以耦合到单线接口的处理电路的装置，该单线接口提供电源电压电平上的两个信号和功率的电气通信。还提供了一个连接在第一源极/ 还提供了一种电荷存储装置，其在连接点处连接到晶体管的第二源极/漏极端子，并且在所述连接点处连接到处理电路的电力输入端口。还有一种控制装置，其具有 耦合到单线接口的输入，耦合到晶体管的栅极的控制输出，并且由连接点处的电荷存储装置供电，使得当单线接口电压处于 电源电压电平。

公开(公告)号：WO2005065137A2

公开(公告)日：2005-07-21

申请号：PCT/US2004/041280

申请日：2004-12-09

申请人： ATMEL CORPORATION

发明人： NG, Philip, S. ,  TSAI, Jeff, Ming-Hung ,  CHAN, Johnny

IPC分类号： H03K17/22

CPC分类号： H03K17/223

摘要： An auto-grounding circuit responsive to a reset signal (PORL) discharges an input terminal (11) of an integrated circuit and its associated input line (13) to ground, using a pull-down transistor (17) coupled to the input line, with a gate of the pull-down transistor coupled to receive the reset signal. An exemplary circuit also includes a NAND gate (25) and a second pull­-down transistor (27) to maintain an established voltage level of the input line after the reset signal is no longer asserted until the input terminal is driven by an applied input signal. The voltage maintaining circuitry is weaker than the main pull-down transistor to avoid interfering with normal operation of the input terminal.

摘要翻译： 响应于复位信号（PORL）的自动接地电路使用耦合到输入线的下拉晶体管（17）将集成电路的输入端（11）及其相关联的输入线（13）放电到地， 其中所述下拉晶体管的栅极被耦合以接收所述复位信号。 示例性电路还包括NAND门（25）和第二下拉晶体管（27），以在复位信号不再断言之后保持输入线的建立电压电平，直到输入端子被施加的输入信号驱动 。 电压保持电路比主下拉晶体管弱，以避免干扰输入端子的正常工作。

公开(公告)号：WO2004109751A3

公开(公告)日：2004-12-16

申请号：PCT/US2004/014693

申请日：2004-05-11

申请人： ATMEL CORPORATION

发明人： NG, Philip, S.

IPC分类号： G06F11/00

摘要： A fault tolerant data storage circuit for an integrated circuit produces a specified initial output state (D out ) with high probability even in the presence of abnormal start-up conditions affecting one or more signal inputs to the storage circuit. The storage circuit includes a plurality of storage elements (10 1 , 10 2 ,...), such as flip-flops, latches, or static RAM cells, each acting as a redundant element for the others. The storage elements are constructed to normally assume a preferred initial state. All storage elements are clocked by a common clock line (12) and loaded at their data inputs (D) from a common data input line (14) of the storage circuit. A logic gate (16), such as an AND gate combines the storage element outputs (Q) and outputs (20) the correct initial state, unless all storage elements happen to be in the wrong state, which is an extremely low probability event.

公开(公告)号：WO2007127700A3

公开(公告)日：2007-11-08

申请号：PCT/US2007/067219

申请日：2007-04-23

申请人： ATMEL CORPORATION ,  NG, Philip, S. ,  SON, Jinshu

发明人： NG, Philip, S. ,  SON, Jinshu

IPC分类号： G06F13/00

摘要： A dual-wire communications bus circuit, compatible with existing two-wire protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line (DATA) for carrying data signals from a master device (301) to a slave device (303) and a second line to carry a clock signal (CLK) between the devices (301, 303). To improve data throughput and reduce noise, an active pullup device is located in at least one part of the communications bus circuit, the active pullup device (305B) in the first part of the communications bus circuit couples to the first line and an optional active pullup device (309A) in the second part couples to the second line of the communications bus. Each active pullup device (305B, 305A) may provide a high logic level on one of the communications bus lines.

公开(公告)号：WO2007065108A2

公开(公告)日：2007-06-07

申请号：PCT/US2006/061349

申请日：2006-11-29

申请人： ATMEL CORPORATION ,  NG, Philip, S. ,  SON, Jinshu ,  CHAN, Johnny

发明人： NG, Philip, S. ,  SON, Jinshu ,  CHAN, Johnny

IPC分类号： G11C11/34

CPC分类号： G11C5/145 ,  G11C5/147

摘要： A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high- voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third high-voltage output circuit is configured to set the output voltage of the charge pump at a third voltage level selected for guardband programming and erasing, the third voltage level being lower than the second voltage level and higher than the first voltage level. Selection circuitry selectively couples one of the first, second, and third high- voltage output circuits to the output of the high-voltage charge pump circuit.

摘要翻译： 高压电荷泵电路包括电荷泵电路。 第一高压输出电路被配置为将电荷泵的输出电压设置为为常规编程而选择的第一电压电平并擦除存储器单元。 第二高压输出电路被配置为将电荷泵的输出电压设置在为器件结的迂回选择的第二电压电平，第二电压电平高于第一电压电平。 第三高压输出电路被配置为将电荷泵的输出电压设置为选择用于保护带编程和擦除的第三电压电平，第三电压电平低于第二电压电平并高于第一电压电平。 选择电路将第一，第二和第三高压输出电路中的一个选择性地耦合到高压电荷泵电路的输出。

公开(公告)号：WO2006138003A1

公开(公告)日：2006-12-28

申请号：PCT/US2006/018482

申请日：2006-05-12

申请人： ATMEL CORPORATION ,  SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

发明人： SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

IPC分类号： G11C8/12

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C2207/002

摘要： A bitline selection network (300; 500) is composed of a plurality of bitlines (BLn7, ..., BLOO) and one or more global bitlines (GBL7, ..., GBLO; GBL) . The bitlines are grouped into bytes (BYTEn, ..., BYTEO) with eight bitlines per byte. The bitlines provide access to memory cells for read and write operations. A bitline is connected to a global bitline through a bitline select transistor (BLSTn7, ..., BLSTOO) . Each of the bitline select transistors is activated (BLSn7, ..., BLSOO) one at a time by a bitline select controller (350) . Global bitlines may be connected through bit select transistors (BST7, ..., BSTO) and activated one at a time by a bit select controller (385) to a source line (388; 588) , which in turn connects to a sense amplifier (395) and a write data loading logic block (390) . The sense amplifier and the write data loading logic block are used in read and write operations respectively.

摘要翻译： 位线选择网络（300; 500）由多个位线（BLn7，...，BLOO）和一个或多个全局位线（GBL7，...，GBLO; GBL）组成。 每个字节有八个位线，将位线分成字节（BYTEn，...，BYTEO）。 位线提供对存储器单元的访问以进行读取和写入操作。 位线通过位线选择晶体管（BLSTn7，...，BLSTOO）连接到全局位线。 每个位线选择晶体管由位线选择控制器（350）一次激活（BLSn7，...，BLSOO）。 全局位线可以通过位选择晶体管（BST7，...，BSTO）连接，并通过位选择控制器（385）一次激活到源极线（388; 588），源极线（388; 588）又连接到读出放大器 （395）和写数据加载逻辑块（390）。 读写放大器和写数据加载逻辑块分别用于读写操作。

公开(公告)号：WO2007018985A2

公开(公告)日：2007-02-15

申请号：PCT/US2006/027914

申请日：2006-07-18

申请人： ATMEL CORPORATION ,  CHAN, Johnny ,  SON, Jinshu ,  NG, Philip, S.

发明人： CHAN, Johnny ,  SON, Jinshu ,  NG, Philip, S.

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/28

摘要： An array (200; 202) of memory cells having a predetermined group (301) of storage cells (203; 205; 306) , arranged in a row, also have an arrangement of one or more reference cells (201; 207; 304, 307) fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or programmed when the storage cells are written to, erased, or programmed. The same number of write, erase, or program cycles and the proximity of the reference cells to the storage cells maintain an operational matching of the storage cells and reference cells.

摘要翻译： 具有排列成行的预定组（301）存储单元（203; 205; 306）的存储器单元的阵列（200; 202）也具有一个或多个参考 制造成与该行存储单元相邻或邻近的单元（201; 207; 304,307）。 当存储单元被写入，擦除或编程时，参考单元被写入，擦除或编程。 相同数量的写入，擦除或编程周期以及参考单元与存储单元的接近度保持存储单元和参考单元的操作匹配。