公开(公告)号：WO2008008613A8

公开(公告)日：2008-01-17

申请号：PCT/US2007/071941

申请日：2007-06-22

申请人： ATMEL CORPORATION ,  CHAN, Johnny

发明人： CHAN, Johnny ,  SON, Jinshu

IPC分类号： G11C11/34

摘要： An improved cross-coupled CMOS high-voltage latch (100) that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit (116) that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg of the latch and ground to limit leakage current. A large number of latches are connected in parallel and their accumulated leakage currents are limited by the switching circuit (116) to prevent overload of a high-voltage generator, such as a charge pump circuit, for the high- voltage latch (100), so that data can be properly written in the memory cells of the non-volatile memory.

公开(公告)号：WO2006020357A1

公开(公告)日：2006-02-23

申请号：PCT/US2005/026205

申请日：2005-07-25

申请人： ATMEL CORPORATION

发明人： SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

IPC分类号： G11C16/04

CPC分类号： G11C17/18 ,  G11C16/20 ,  G11C2216/30

摘要： Fuse data used to configure ancillary circuits (81) used with a non-volatile serial memory core (51) are stored in locations (54) within the memory core. As a first opcode or word is sent on a serial bus (61) to the memory, a logic circuit (67, 75, 77) intercepts the word and generates read fuse enable pulses that fetch the fuse data and configure the ancillary circuits before the last bit of the first command byte arrives. If a read operation is designated, the memory circuits are configured to read. If a write operation is designated, further fuse data is fetched from the memory core to configure ancillary circuits for writing. The fuse data is written to the memory core at the time of circuit manufacture thereby obviating the need for separate storage locations.

摘要翻译： 用于配置与非易失性串行存储器核心（51）一起使用的辅助电路（81）的保险丝数据被存储在存储器核心内的位置（54）中。 当串行总线（61）上的第一个操作码或字被发送到存储器时，逻辑电路（67,75,77）拦截该字并产生读保险丝使能脉冲，其获取保险丝数据并在辅助电路之前配置 第一个命令字节的最后一位到达。 如果指定了读取操作，则存储器电路被配置为读取。 如果指定写入操作，则从存储器核心获取进一步的熔丝数据以配置用于写入的辅助电路。 在电路制造时，熔丝数据被写入存储器核心，从而避免了对单独的存储位置的需要。

公开(公告)号：WO2007124304A2

公开(公告)日：2007-11-01

申请号：PCT/US2007/066779

申请日：2007-04-17

申请人： ATMEL CORPORATION ,  NG, Philip, S. ,  SON, Jinshu

发明人： NG, Philip, S. ,  SON, Jinshu

IPC分类号： H03K19/003

CPC分类号： H03K19/01721 ,  H03K19/01742

摘要： A dual -wire communications bus circuit (300), compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit (300) to couple to a communications bus (317). The bus (317) has a first line for carrying data signals from a master device (201) to one or more slave devices (315A- 315H) and a second line to carry a clock signal between the devices (315A-315H). A pullup resistor (305, 311) is located in each part of the communications bus circuit (300); the pullup resistor (305) in the first part couples to the first line of the communications bus (317) and the pullup resistor (311) in the second part couples to the second line of the communications bus (317). To improve data throughput and reduce noise, an active pullup device (301A2-301H2), working in conjunction with the pullup resistor (311), is located in each part of the communications bus circuit (300), providing a high logic level on at least one of the communications bus lines.

摘要翻译： 与现有的双线总线协议兼容的双线通信总线电路（300）包括通信总线电路（300）的第一和第二部分，以耦合到通信总线（317）。 总线（317）具有用于将数据信号从主设备（201）传送到一个或多个从设备（315A-315H）的第一线路和用于在设备（315A-315H）之间传送时钟信号）的第二线路。 上拉电阻（305,311）位于通信总线电路（300）的每个部分中; 第一部分中的上拉电阻（305）耦合到通信总线（317）的第一行，并且第二部分中的上拉电阻（311）耦合到通信总线（317）的第二行。 为了提高数据吞吐量并降低噪声，与通信总线电路（300）的每个部分中位于与上拉电阻器（311）一起工作的有源上拉器件（301A2-301H2），提供高逻辑电平 至少有一条通信总线。

公开(公告)号：WO2007127700A3

公开(公告)日：2007-11-08

申请号：PCT/US2007/067219

申请日：2007-04-23

申请人： ATMEL CORPORATION ,  NG, Philip, S. ,  SON, Jinshu

发明人： NG, Philip, S. ,  SON, Jinshu

IPC分类号： G06F13/00

摘要： A dual-wire communications bus circuit, compatible with existing two-wire protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line (DATA) for carrying data signals from a master device (301) to a slave device (303) and a second line to carry a clock signal (CLK) between the devices (301, 303). To improve data throughput and reduce noise, an active pullup device is located in at least one part of the communications bus circuit, the active pullup device (305B) in the first part of the communications bus circuit couples to the first line and an optional active pullup device (309A) in the second part couples to the second line of the communications bus. Each active pullup device (305B, 305A) may provide a high logic level on one of the communications bus lines.

公开(公告)号：WO2007065108A2

公开(公告)日：2007-06-07

申请号：PCT/US2006/061349

申请日：2006-11-29

申请人： ATMEL CORPORATION ,  NG, Philip, S. ,  SON, Jinshu ,  CHAN, Johnny

发明人： NG, Philip, S. ,  SON, Jinshu ,  CHAN, Johnny

IPC分类号： G11C11/34

CPC分类号： G11C5/145 ,  G11C5/147

摘要： A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high- voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third high-voltage output circuit is configured to set the output voltage of the charge pump at a third voltage level selected for guardband programming and erasing, the third voltage level being lower than the second voltage level and higher than the first voltage level. Selection circuitry selectively couples one of the first, second, and third high- voltage output circuits to the output of the high-voltage charge pump circuit.

摘要翻译： 高压电荷泵电路包括电荷泵电路。 第一高压输出电路被配置为将电荷泵的输出电压设置为为常规编程而选择的第一电压电平并擦除存储器单元。 第二高压输出电路被配置为将电荷泵的输出电压设置在为器件结的迂回选择的第二电压电平，第二电压电平高于第一电压电平。 第三高压输出电路被配置为将电荷泵的输出电压设置为选择用于保护带编程和擦除的第三电压电平，第三电压电平低于第二电压电平并高于第一电压电平。 选择电路将第一，第二和第三高压输出电路中的一个选择性地耦合到高压电荷泵电路的输出。

公开(公告)号：WO2006138003A1

公开(公告)日：2006-12-28

申请号：PCT/US2006/018482

申请日：2006-05-12

申请人： ATMEL CORPORATION ,  SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

发明人： SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

IPC分类号： G11C8/12

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C2207/002

摘要： A bitline selection network (300; 500) is composed of a plurality of bitlines (BLn7, ..., BLOO) and one or more global bitlines (GBL7, ..., GBLO; GBL) . The bitlines are grouped into bytes (BYTEn, ..., BYTEO) with eight bitlines per byte. The bitlines provide access to memory cells for read and write operations. A bitline is connected to a global bitline through a bitline select transistor (BLSTn7, ..., BLSTOO) . Each of the bitline select transistors is activated (BLSn7, ..., BLSOO) one at a time by a bitline select controller (350) . Global bitlines may be connected through bit select transistors (BST7, ..., BSTO) and activated one at a time by a bit select controller (385) to a source line (388; 588) , which in turn connects to a sense amplifier (395) and a write data loading logic block (390) . The sense amplifier and the write data loading logic block are used in read and write operations respectively.

摘要翻译： 位线选择网络（300; 500）由多个位线（BLn7，...，BLOO）和一个或多个全局位线（GBL7，...，GBLO; GBL）组成。 每个字节有八个位线，将位线分成字节（BYTEn，...，BYTEO）。 位线提供对存储器单元的访问以进行读取和写入操作。 位线通过位线选择晶体管（BLSTn7，...，BLSTOO）连接到全局位线。 每个位线选择晶体管由位线选择控制器（350）一次激活（BLSn7，...，BLSOO）。 全局位线可以通过位选择晶体管（BST7，...，BSTO）连接，并通过位选择控制器（385）一次激活到源极线（388; 588），源极线（388; 588）又连接到读出放大器 （395）和写数据加载逻辑块（390）。 读写放大器和写数据加载逻辑块分别用于读写操作。

公开(公告)号：WO2007115120A2

公开(公告)日：2007-10-11

申请号：PCT/US2007/065539

申请日：2007-03-29

申请人： ATMEL CORPORATION ,  WANG, Liqi ,  SON, Jinshu ,  NG, Philip ,  CHAN, Johnny

发明人： WANG, Liqi ,  SON, Jinshu ,  NG, Philip ,  CHAN, Johnny

IPC分类号： A23J1/02

CPC分类号： G01R31/40 ,  G01R31/3004

摘要： Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.

摘要翻译： 用于测试集成电路中的上电复位电路的电路包括耦合到集成电路的第一I / O焊盘的高电压检测器。 集成电路中的上电复位电路具有耦合到由高电压供电的驱动器电路的输出。 集成电路的第二I / O焊盘耦合到驱动器电路的输出端。 可以通过集成电路的第三I / O焊盘上提供的信号使能驱动器电路。

公开(公告)号：WO2007018985A2

公开(公告)日：2007-02-15

申请号：PCT/US2006/027914

申请日：2006-07-18

申请人： ATMEL CORPORATION ,  CHAN, Johnny ,  SON, Jinshu ,  NG, Philip, S.

发明人： CHAN, Johnny ,  SON, Jinshu ,  NG, Philip, S.

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/28

摘要： An array (200; 202) of memory cells having a predetermined group (301) of storage cells (203; 205; 306) , arranged in a row, also have an arrangement of one or more reference cells (201; 207; 304, 307) fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or programmed when the storage cells are written to, erased, or programmed. The same number of write, erase, or program cycles and the proximity of the reference cells to the storage cells maintain an operational matching of the storage cells and reference cells.

摘要翻译： 具有排列成行的预定组（301）存储单元（203; 205; 306）的存储器单元的阵列（200; 202）也具有一个或多个参考 制造成与该行存储单元相邻或邻近的单元（201; 207; 304,307）。 当存储单元被写入，擦除或编程时，参考单元被写入，擦除或编程。 相同数量的写入，擦除或编程周期以及参考单元与存储单元的接近度保持存储单元和参考单元的操作匹配。

公开(公告)号：WO2006110239A1

公开(公告)日：2006-10-19

申请号：PCT/US2006/008448

申请日：2006-03-08

申请人： ATMEL CORPORATION ,  SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

发明人： SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

IPC分类号： G11C7/10

CPC分类号： G11C8/10 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048

摘要： A multiplexer circuit in a memory organized into page-portions (210, 250) has a plurality of bit- select multiplexers (216, 256) configured to couple a plurality of page-portion global bitlines (214, 254) to a sense amplifier (201) input. A plurality of column address lines organized into data bytes comprises each page-portion. A plurality of column multiplexers (212, 252) couple the data bytes to the page-portion global bitlines (214, 254) such that each of the address lines comprising the data byte is coupled to one of the page-portion global bitlines (214, 254).

摘要翻译： 被组织成页面部分（210,250）的存储器中的多路复用器电路具有多个位选择多路复用器（216,256），其被配置为将多个页面部分全局位线（214,254）耦合到读出放大器 201）输入。 组织成数据字节的多个列地址线包括每个页面部分。 多个列复用器（212,252）将数据字节耦合到页面部分全局位线（214,254），使得包括数据字节的每个地址线被耦合到页面部分全局位线之一（214 ，254）。

公开(公告)号：WO2005006394A2

公开(公告)日：2005-01-20

申请号：PCT/US2004/017820

申请日：2004-06-07

申请人： ATMEL CORPORATION

发明人： NG, Philip, S. ,  YE, Ken Kun ,  SON, Jinshu

IPC分类号： H01L

CPC分类号： G11C29/021 ,  G01R31/3004 ,  G11C5/147 ,  G11C8/08 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  H03K3/0375 ,  H03K3/356008

摘要： A switch controlling circuit for the testing and fine-tuning of integrated circuits comprising of a series of flip-flops (30, 32, ..., 34) chained together in a serial manner. The contents of the flip-flop are shifted in from an input (38) leading to the first flip­flop (30) in the chain. The output of each flip-flop connects to individual transistor switch (F 1 , F 2 , ..., F n ) whereby the states of the flip-flops control the state of the switches. Circuitry (50, 52, ..., 54) for establishing a default state of the switches may be provided.

摘要翻译： 一种用于集成电路的测试和微调的开关控制电路，包括串联连接在一起的一系列触发器（30,32，...，34）。 触发器的内容从通向链中的第一触发器（30）的输入（38）移入。 每个触发器的输出连接到单独的晶体管开关（F1，F2，...，Fn），由此触发器的状态控制开关的状态。 可以提供用于建立开关的默认状态的电路（50,52，...，54）。