公开(公告)号：WO2014020479A3

公开(公告)日：2014-04-10

申请号：PCT/IB2013055946

申请日：2013-07-19

Applicant: ECOLE POLYTECH

Inventor： GUIDUCCI CARLOTTA ,  LEBLEBICI YUSUF ,  TEMIZ YÜKSEL

IPC: H01L21/60 ,  H01L21/683 ,  H01L21/768 ,  H01L21/98 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/50 ,  G03F7/2022 ,  G03F7/32 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3185 ,  H01L24/02 ,  H01L24/05 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68381 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/27002 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82002 ,  H01L2224/82005 ,  H01L2224/8201 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/82143 ,  H01L2224/83143 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/00013 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method for performing a post processing patterning on a diced chip having a footprint, comprises the steps of: - providing a support wafer; - applying a first dry film photoresist to the support wafer; - positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; - exposing the mask and the first dry film photoresist to UV radiation; - removing the mask; - developing the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; - positioning the diced chip inside the cavity; - applying a second dry film photoresist to the first film photoresist and the diced chip; - exposing and developing the second dry film photoresist applied to the diced chip in accordance with the post processing pattern; and - performing an anisotropic dry etching of the chip to form a via therein. Furthermore, a method for obtaining a stack of two semiconductor chips or wafers in a back to face configuration, whereby at least one of the semiconductor chips or wafers comprises a through silicon via (TSV), comprises the steps of: - providing a first semiconductor chip or wafer; - providing a second semiconductor chip or wafer; - making a hole through the second semiconductor chip or wafer from a face side to a back side; - applying the face side of second semiconductor chip or wafer on a release tape; - depositing parylene on the assembly of the second semiconductor chip or wafer and the release tape, thereby obtaining a sidewall passivation in the hole and a bonding layer on the back side of the second semiconductor chip or wafer; - releasing the release tape, thereby obtaining a membrane of parylene covering an opening of the hole on the front side; - positioning the back side of the second semiconductor chip or wafer relative to a face side of the first semiconductor chip or wafer; - bonding the second semiconductor chip or wafer to the first semiconductor chip or wafer by applying pressure and heat; - removing the membrane of parylene by directional etching; and - electrically connecting the face side of the second semiconductor chip or wafer to the face side of the first semiconductor chip or wafer by depositing a conductor inside the hole, thereby obtaining the TSV.

Abstract translation: 一种用于在具有占地面积的切割芯片上执行后处理图案化的方法包括以下步骤： - 提供支撑晶片; - 将第一干膜光致抗蚀剂施加到所述支撑晶片; - 将对应于切割芯片的覆盖区的掩模定位在第一干膜光致抗蚀剂上; - 将所述掩模和所述第一干膜光致抗蚀剂暴露于UV辐射; - 去除面膜; - 将暴露的第一干膜光致抗蚀剂显影以获得对应于切割芯片的腔; - 将切割的芯片定位在腔内; - 将第二干膜光致抗蚀剂施加到第一膜光致抗蚀剂和切割的芯片上; - 根据后处理图案曝光和显影施加到切割的芯片上的第二干膜光致抗蚀剂; 以及 - 对所述芯片进行各向异性干蚀刻以在其中形成通孔。 此外，一种用于以背对面配置获得两个半导体芯片或晶片的堆叠的方法，由此半导体芯片或晶片中的至少一个包括贯穿硅通孔（TSV），包括以下步骤： - 提供第一半导体 芯片或晶片; - 提供第二半导体芯片或晶片; - 从第二半导体芯片或晶片从正面到背面形成一个孔; - 将第二半导体芯片或晶片的表面施加在释放带上; - 将聚对二甲苯沉积在第二半导体芯片或晶片和释放带的组件上，从而在孔中获得侧壁钝化和在第二半导体芯片或晶片的背面上的结合层; - 释放释放带，从而获得覆盖前侧的孔的开口的聚对二甲苯膜; - 相对于所述第一半导体芯片或晶片的正面侧定位所述第二半导体芯片或晶片的背面; - 通过施加压力和热量将所述第二半导体芯片或晶片接合到所述第一半导体芯片或晶片; - 通过定向蚀刻去除聚对二甲苯膜; 以及 - 通过在孔内沉积导体，将第二半导体芯片或晶片的表面侧电连接到第一半导体芯片或晶片的正面，从而获得TSV。