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    FINE-PITCH FLEXIBLE WIRING
    5.
    发明申请
    FINE-PITCH FLEXIBLE WIRING 审中-公开
    精细接线灵活接线

    公开(公告)号：WO2013181000A2

    公开(公告)日：2013-12-05

    申请号：PCT/US2013/041750

    申请日：2013-05-20

    Applicant: GENERAL ELECTRIC COMPANY

    Inventor： ROSE, James, Wilson ,  NAGARKAR, Kaustubh, Ravindra ,  GALLIGAN, Craig, Patrick ,  SHAH, Binoy, Milan ,  ASTLEY, Oliver, Richard

    IPC: H02G15/02 ,  H01B13/00

    CPC classification number: H01L24/43 ,  H01L24/46 ,  H01L2224/43 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H05K1/118 ,  H05K2203/0235 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

    Abstract: A flexible wire assembly includes a plurality of elongated conductors and insulators each having a quadrilateral cross section and alternatingly laminated together, the flexible wire assembly having a wire width measured across the conductor and insulators, a wire height equivalent to the height of the conductors and insulators, and a wire length which is measured in a longitudinal direction orthogonal to the wire width and the wire height, wherein the wire length is one or more orders of magnitude greater than the wire width and the wire height; and a first device comprising a plurality of bond pads spaced to define a bond pad pitch, wherein the flexible wire assembly is coupled to the first device at the bond pads such that spacing of the conductor conductors is matched to the bond pad pitch.

    Abstract translation: 柔性线组件包括多个细长导体和绝缘体，每个细长导体和绝缘体具有四边形横截面并交替层压在一起，柔性线组件具有跨导体和绝缘体测量的导线宽度，线高度等于导体和绝缘体的高度 以及在与线宽度和线高度正交的纵向方向上测量的线长度，其中线长度比线宽和线高度大一个或多个数量级; 以及包括间隔开以限定接合焊盘间距的多个接合焊盘的第一器件，其中所述柔性线组件在所述接合焊盘处耦合到所述第一器件，使得所述导体导体的间隔与所述接合焊盘间距匹配。

    ELECTRONICS PACKAGE HAVING A SELF-ALIGNING INTERCONNECT ASSEMBLY AND METHOD OF MAKING SAME
    6.
    发明申请
    ELECTRONICS PACKAGE HAVING A SELF-ALIGNING INTERCONNECT ASSEMBLY AND METHOD OF MAKING SAME 审中-公开

    公开(公告)号：WO2019032211A1

    公开(公告)日：2019-02-14

    申请号：PCT/US2018/039464

    申请日：2018-06-26

    Applicant: GENERAL ELECTRIC COMPANY

    Inventor： KAPUSTA, Christopher, James ,  NAGARKAR, Kaustubh, Ravindra ,  GOWDA, Arun, Virupaksha ,  ROSE, James, Wilson

    IPC: H01L23/485 ,  H01L23/498 ,  H01L23/528 ,  H01L23/14

    Abstract: An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

    METHOD OF MANUFACTURING AN ELECTRONICS USING DEVICE-LAST OFR DEVICE-ALMOST LAST PLACEMENT
    9.
    发明申请
    METHOD OF MANUFACTURING AN ELECTRONICS USING DEVICE-LAST OFR DEVICE-ALMOST LAST PLACEMENT 审中-公开

    公开(公告)号：WO2019032313A1

    公开(公告)日：2019-02-14

    申请号：PCT/US2018/044101

    申请日：2018-07-27

    Applicant: GENERAL ELECTRIC COMPANY

    Inventor： KAPUSTA, Christopher, James ,  FILLION, Raymond, Albert ,  TUOMINEN, Risto Ilkka, Sakari ,  NAGARKAR, Kaustubh, Ravindra

    IPC: H01L23/13 ,  H01L23/14 ,  H01L23/00 ,  H01L23/48

    Abstract: A method of manufacturing a multi-layer electronics package includes attaching a base insulating substrate to a frame having an opening therein and such that the frame is positioned above and/or below the base insulating substrate to provide support thereto. A first conductive wiring layer is applied on the first side of the base insulating substrate, and vias are formed in the base insulating substrate. A second conductive wiring layer is formed on the second side of the base insulating substrate that covers the vias and the exposed portions of the first conductive wiring layer and at least one additional insulating substrate is bonded to the base insulating substrate. Vias are formed in each additional insulating substrate and an additional conductive wiring layer is formed on each of the additional insulating substrate. The described build-up forms a multilayer interconnect structure, with the frame providing support for this build-up.

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