公开(公告)号：WO2018160179A1

公开(公告)日：2018-09-07

申请号：PCT/US2017/020293

申请日：2017-03-01

Applicant: INTEL CORPORATION

Inventor： MEKONNEN, Yidnekachew S. ,  AYGUN, Kemal ,  BRAUNISCH, Henning

IPC: H04B3/32 ,  H04L25/08 ,  H05K1/02

Abstract: Technology for simplified multimode signaling includes determining first and second self α-terms, cross coupling α-terms, and a delay skew term. For each communication link bundled in groups, the signals can be modulated as a superposition of the signals delayed and weighted based on the first and second self α-terms, the cross coupling α-terms and the delay skew term.

公开(公告)号：WO2018004851A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/032940

申请日：2017-05-16

Applicant: INTEL CORPORATION

Inventor： ZHANG, Yu Amos ,  KIM, Jihwan ,  BALANKUTTY, Ajay ,  SRIRAMULU, Anupriya ,  MAZUMDER, MD. Mohiuddin ,  O'MAHONY, Frank ,  WU, Zuoguo ,  AYGUN, Kemal

IPC: H01L23/62 ,  H01L49/02 ,  H01L23/64

Abstract: Integrated circuit (IC) chip "on-die" inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.

Abstract translation: 集成电路（IC）芯片“片上”（on-die） 电感器结构（用于其制造的系统和方法）可以改善从数据信号电路到芯片的表面接触的信号传输。 这样的电感器结构可以包括具有（1）电耦合到静电放电（ESD）电路的第二端和该电路的电容值的第一数据信号电感器，以及（2）电耦合到数据信号表面 接触并达到该接触处的电容值; 以及第二数据信号电感器，其具有（1）电耦合到数据信号电路的第二端和该电路的电容值，（2）电耦合到第一数据信号电感器的第二端的第一端，以及 ESD电路的电容值。 可以选择第一和第二电感器的电感值以消除电容值以改善信号传输。

公开(公告)号：WO2017111957A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/067447

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： QIAN, Zhiguo ,  XIE, Jianyong ,  AYGUN, Kemal

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/48

CPC classification number: H01L24/20 ,  H01L25/065 ,  H01L25/07 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014

Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.

Abstract translation: 公开了具有穿通桥芯片连接的半导体封装及其制造方法。 半导体封装可以容纳一个或多个电子组件作为封装（SiP）实现中的系统。 诸如嵌入式多芯片互连桥（EMIB）之类的桥接管芯可嵌入半导体封装的一个或多个构建层内。 桥接管芯可以具有导电块，其可以在背侧电连接到电源平面并且用于经由形成在桥接管芯的顶侧上的互连而将电力递送到附接到半导体封装的一个或多个管芯，电桥 到桥模的大部分。 与在桥芯片周围路由功率相比，可以实现通过桥芯片传输功率的更直接路径。

公开(公告)号：WO2017111855A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000431

申请日：2015-12-26

Applicant: INTEL CORPORATION

Inventor： ZHANG, Yu, Amos ,  MANUSHAROW, Mathew, J. ,  AYGUN, Kemal ,  MAZUMDER, Mohiuddin

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L23/50 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/13101 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/17515 ,  H01L2224/81801 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.

Abstract translation: 接地隔离带状结构封装包括具有上互连层的顶层，所述上互连层具有上接地触点，上数据信号触点以及连接到所述上接地触点的导电材料上接地带状结构，以及 围绕上部数据信号触点。 上触点可以形成在相同互连层的下层的通孔触点或迹线上并连接到该通孔触点或迹线。 下层的通孔触点可以连接到也可以具有这种织带的第二互连级的上触点。 也可能有至少一个具有这种织带的第三互连层。 该带状结构电隔离并减少信号触点之间的串扰，从而在诸如附接到封装的集成电路（IC）芯片之类的器件之间提供更高频率和更精确的数据信号传输。

公开(公告)号：WO2017052815A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/046140

申请日：2016-08-09

Applicant: INTEL CORPORATION

Inventor： LEE, Beom-Taek ,  ATHREYA, Dhanya ,  AYGUN, Kemal ,  BASTOLA, Subas

IPC: H05K1/02 ,  H03H7/40

CPC classification number: H01P5/028

Abstract: One embodiment provides an apparatus. The apparatus includes an impedance matching interconnect having a first end and a second end. The impedance matching interconnect includes an interface trace having a first width at the first end and a second width at the second end, the first width less than the second width. The impedance matching interconnect further includes a first dielectric layer adjacent the interface trace; a first reference plane adjacent the first dielectric layer; at least one via adjacent the first reference plane; and a second reference plane adjacent the at least one via, the at least one via to couple the first reference plane and the second reference plane. A first distance between the interface trace and the first reference plane is less than a second distance between the interface trace and the second reference plane.

Abstract translation: 一个实施例提供了一种装置。 该装置包括具有第一端和第二端的阻抗匹配互连。 阻抗匹配互连包括在第一端具有第一宽度和第二端的第二宽度的接口迹线，第一宽度小于第二宽度。 阻抗匹配互连还包括与界面迹线相邻的第一电介质层; 邻近第一介电层的第一参考平面; 邻近第一参考平面的至少一个通孔; 以及与所述至少一个通孔相邻的第二参考平面，所述至少一个通孔耦合所述第一参考平面和所述第二参考平面。 界面轨迹和第一参考平面之间的第一距离小于界面轨迹和第二参考平面之间的第二距离。

公开(公告)号：WO2018174869A1

公开(公告)日：2018-09-27

申请号：PCT/US2017/023575

申请日：2017-03-22

Applicant: INTEL CORPORATION

Inventor： MEKONNEN, Yidnekachew S. ,  AYGUN, Kemal ,  MAHAJAN, Ravindranath V. ,  BALDWIN, Christopher S. ,  SWAMINATHAN, Rajasekaran

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/58

Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

公开(公告)号：WO2018118329A1

公开(公告)日：2018-06-28

申请号：PCT/US2017/062847

申请日：2017-11-21

Applicant: INTEL CORPORATION

Inventor： WENG, Li-Sheng ,  CHEN, Chung-Hao Joseph ,  DAVIES-VENN, Emile ,  AYGUN, Kemal ,  MODI, Mitul B.

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/485 ,  H01L23/522

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：WO2017172224A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/020273

申请日：2017-03-01

Applicant: INTEL CORPORATION

Inventor： OSTER, Sasha N. ,  ELSHERBINI, Adel A. ,  AYGUN, Kemal ,  SANKMAN, Robert L.

IPC: H01P3/02

CPC classification number: H01P3/06 ,  G06F1/16 ,  H01B11/1891 ,  H01P3/02

Abstract: Electrical cable technology is disclosed. In one example, an electrical cable can include a transmission line conductor, a ground conductor, and a dielectric material. The dielectric material can have at least a portion with a thickness separating the transmission line conductor and the ground conductor that is variable along a length of the electrical cable. Such a non-uniform cable (e.g., a cable having components or features that vary in size and/or geometry along the length of the cable) can provide high IO density with acceptable conductive losses and cross-talk while maintaining a desired impedance.

Abstract translation: 公开了电缆技术。 在一个示例中，电缆可以包括传输线导体，接地导体和电介质材料。 介电材料可以具有至少一部分，该部分具有将传输线导体和接地导体分开的厚度，该厚度沿着电缆的长度是可变的。 这样的非均匀电缆（例如，具有沿着电缆的长度在尺寸和/或几何形状上变化的部件或特征的电缆）可以在保持期望的阻抗的同时提供具有可接受的导电损耗和串扰的高IO密度。 / p>

公开(公告)号：WO2017112101A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/060153

申请日：2016-11-02

Applicant: INTEL CORPORATION

Inventor： ZHANG, Yu ,  MANUSHAROW, Mathew J. ,  ELSHERBINI, Adel A. ,  BRAUNISCH, Henning ,  AYGUN, Kemal

IPC: H01L25/16 ,  H01L25/18 ,  H01L21/027 ,  H01L23/58

CPC classification number: H04B3/32 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: Embodiments are generally directed to a shielded bundle interconnect. An embodiment of an apparatus includes multiple signal bundles, the signal bundles including a first signal bundle including a first plurality of signals and a second signal bundle including a second plurality of signals; and a lithographic via shielding to provide electromagnetic shielding, the lithographic via shielding located at least in part between the first signal bundle and the second signal bundle, wherein the lithographic via shielding includes at least a via generated by a lithographic via process. The lithographic via shielding partially or completely surrounds at least one of the signal bundles of the apparatus.

Abstract translation: 实施例通常针对屏蔽束互连。 一种设备的实施例包括多个信号束，所述信号束包括包含第一多个信号的第一信号束和包含第二多个信号的第二信号束; 以及平版印刷通孔屏蔽以提供电磁屏蔽，所述平版印刷通孔屏蔽至少部分位于所述第一信号束与所述第二信号束之间，其中所述平版印刷通孔屏蔽包括至少一个通过平版印刷通孔工艺产生的通孔。 光刻通孔屏蔽部分地或完全地包围设备的至少一个信号束。

公开(公告)号：WO2017111823A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000381

申请日：2015-12-26

Applicant: INTEL CORPORATION

Inventor： ZHANG, Yu, Amos ,  REGALADO, Gabriel, S. ,  QIAN, Zhiguo ,  AYGUN, Kemal

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243

Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.

Abstract translation: 接地隔离传输线封装装置包括（1）围绕或（3）这些接地平面周围的接地隔离线与围绕水平数据信号传输的这种接地隔离线之间的接地隔离平面 通过封装器件水平布线的线（例如，金属信号迹线）。 （1）接地隔离线和/或（2）接地隔离线之间的（1）接地隔离平面电屏蔽信号线中传输的数据信号，从而减少数据信号传输线之间的信号串扰并增加电隔离。 另外，可以使用眼图来调谐数据信号传输线以选择提供最佳数据传输性能的信号线宽度和接地隔离线宽度。 该封装器件在数据信号传输线的不同水平位置之间提供更高频率和更准确的数据信号传输，并且因此也在诸如附接到封装器件的集成电路（IC）芯片之类的器件之间提供更高频率和更准确的数据信号传输。