公开(公告)号：WO2014051732A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/045427

申请日：2013-06-12

Applicant: INTEL CORPORATION

Inventor： DASGUPTA, Sansaptak ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  MUKHERJEE, Niloy ,  GOEL, Niti ,  KABEHIE, Sanaz ,  SUNG, Seung Hoon ,  PILLARISETTY, Ravi ,  CHAU, Robert S.

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract translation: 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：WO2013095349A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/065931

申请日：2011-12-19

Applicant: INTEL CORPORATION ,  GILES, Martin, D. ,  CAPPELLANI, Annalisa ,  KABEHIE, Sanaz ,  RIOS, Rafael ,  WEBER, Cory, E. ,  BUDREVICH, Aaron A.

Inventor： GILES, Martin, D. ,  CAPPELLANI, Annalisa ,  KABEHIE, Sanaz ,  RIOS, Rafael ,  WEBER, Cory, E. ,  BUDREVICH, Aaron A.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

Abstract translation: 描述具有金属源极和漏极区域的半导体器件。 例如，半导体器件包括设置在衬底的半导体沟道区域上方的栅电极堆叠。 金属源区和漏区设置在衬底的上方，位于半导体沟道区的任一侧。 金属源极和漏极区域中的每个具有轮廓。 第一半导体外扩散区域设置在衬底中，在半导体沟道区域和金属源极区域之间，并与金属源极区域的形状保持一致。 第二半导体外扩散区域设置在衬底中，在半导体沟道区域和金属漏极区域之间，并与金属漏极区域的轮廓保形。

公开(公告)号：WO2013100914A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067424

申请日：2011-12-27

Applicant: INTEL CORPORATION ,  MUKHERJEE, Niloy ,  DEWEY, Gilbert. ,  RADOSAVLJEVIC, Marko ,  GOEL, Niti ,  KABEHIE, Sanaz ,  METZ, Matthew V. ,  CHAU, Robert S.

Inventor： MUKHERJEE, Niloy ,  DEWEY, Gilbert. ,  RADOSAVLJEVIC, Marko ,  GOEL, Niti ,  KABEHIE, Sanaz ,  METZ, Matthew V. ,  CHAU, Robert S.

IPC: H01L21/28 ,  H01L21/265

CPC classification number: H01L29/41725 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/26513 ,  H01L21/76814 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66628

Abstract: A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet- vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence.

Abstract translation: 芯片包括半导体突起和突出的表面掺杂结构。 表面掺杂结构与接触金属化接触。 突出可能是晶体管的源极或漏极接触。 制造表面掺杂结构的方法包括湿气和注入技术，并且包括退火技术以在表面掺杂仅在半导体突出物中的近表面深度驱动。