公开(公告)号：WO2018125211A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069499

申请日：2016-12-30

申请人： INTEL CORPORATION ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak

发明人： THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak

IPC分类号： H01L27/24 ,  H01L29/51 ,  H01L21/768 ,  H01L29/778

摘要： A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposed adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.

公开(公告)号：WO2016209218A1

公开(公告)日：2016-12-29

申请号：PCT/US2015/037237

申请日：2015-06-23

申请人： INTEL CORPORATION ,  KARPOV, Elijah V. (Ilya) ,  KAVALIEROS, Jack T. ,  CHAU, Robert S. ,  MUKHERJEE, Niloy ,  RIOS, Rafael ,  MAJHI, Prashant ,  LE, Van H. ,  PILLARISETTY, Ravi ,  SHAH, Uday ,  DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko

发明人： KARPOV, Elijah V. (Ilya) ,  KAVALIEROS, Jack T. ,  CHAU, Robert S. ,  MUKHERJEE, Niloy ,  MAJHI, Prashant ,  LE, Van H. ,  PILLARISETTY, Ravi ,  SHAH, Uday ,  DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko

IPC分类号： H01L27/108

CPC分类号： H01L27/108 ,  G11C13/0007 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/2436 ,  H01L27/2472 ,  H01L29/7869 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1633

摘要： A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.

摘要翻译： 在衬底上的金属层的一部分上沉积薄膜晶体管。 存储元件耦合到薄膜晶体管以提供第一存储单元。 第二个存储单元位于第一个存储器之上。 逻辑块至少耦合到第一存储器单元。

公开(公告)号：WO2015147802A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/031741

申请日：2014-03-25

申请人： INTEL CORPORATION ,  THEN, Han Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert

发明人： THEN, Han Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7787

摘要： III-N transistors with epitaxial semiconductor heterostructures having steep subthreshold slope are described. In embodiments, a III-N HFET employs a gate stack with balanced and opposing III-N polarization materials. Overall effective polarization of the opposing III-N polarization materials may be modulated by an external field, for example associated with an applied gate electrode voltage. In embodiments, polarization strength differences between the III-N materials within the gate stack are tuned by composition and/or film thickness to achieve a desired transistor threshold voltage (Vt). With polarization strengths within the gate stack balanced and opposing each other, both forward and reverse gate voltage sweeps may generate a steep sub-threshold swing in drain current as charge carriers are transferred to and from the III-N polarization layers and the III-N channel semiconductor.

摘要翻译： 描述具有陡峭亚阈值斜率的外延半导体异质结构的III-N晶体管。 在实施例中，III-NHFET采用具有平衡和相对的III-N极化材料的栅极叠层。 相对的III-N偏振材料的总体有效极化可以通过外部场来调制，例如与施加的栅电极电压相关联。 在实施例中，栅堆叠内的III-N材料之间的极化强度差异通过组合和/或膜厚来调节以实现期望的晶体管阈值电压（Vt）。 由于栅极堆叠内的极化强度平衡和相互对置，正向和反向栅极电压扫描都可能在漏极电流中产生陡峭的次阈值摆幅，因为电荷载流子传输到III-N偏振层和III-N极化层 通道半导体。

公开(公告)号：WO2013095643A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067220

申请日：2011-12-23

申请人： INTEL CORPORATION ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  SHAH, Uday ,  MUKHERJEE, Niloy ,  PILLARISETTY, Ravi ,  CHU-KUNG, Benjamin ,  KAVALIEROS, Jack ,  CHAU, Robert

发明人： THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  SHAH, Uday ,  MUKHERJEE, Niloy ,  PILLARISETTY, Ravi ,  CHU-KUNG, Benjamin ,  KAVALIEROS, Jack ,  CHAU, Robert

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

摘要翻译： 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和II​​I-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化​​物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

公开(公告)号：WO2013095346A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/065922

申请日：2011-12-19

申请人： INTEL CORPORATION ,  THEN, Han Wui ,  CHAU, Robert ,  CHU-KUNG, Benjamin ,  DEWEY, Gilbert ,  KAVALIEROS, Jack ,  METZ, Matthew V. ,  MUKHERJEE, Niloy ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko

发明人： THEN, Han Wui ,  CHAU, Robert ,  CHU-KUNG, Benjamin ,  DEWEY, Gilbert ,  KAVALIEROS, Jack ,  METZ, Matthew V. ,  MUKHERJEE, Niloy ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

摘要： Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (101 ?0) plane on a (110) plane of the silicon.

摘要翻译： 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性结晶半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，在硅的（110）平面上具有（101→0）面。

公开(公告)号：WO2013095345A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/065921

申请日：2011-12-19

申请人： INTEL CORPORATION ,  THEN, Han Wui ,  CHAU, Robert ,  RAO, Valluri ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  DEWEY, Gilbert ,  KAVALIEROS, Jack

发明人： THEN, Han Wui ,  CHAU, Robert ,  RAO, Valluri ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  DEWEY, Gilbert ,  KAVALIEROS, Jack

IPC分类号： H01L27/00 ,  H01L21/77

CPC分类号： H01L25/072 ,  H01L21/8252 ,  H01L21/8258 ,  H01L25/50 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

摘要翻译： 片上系统（SoC）解决方案使用基于能够实现高Ft和足够高的击穿电压（BV）的III类氮化物（III-N）的晶体管技术将RFIC与PMIC集成，以实现高电压和/ 或高功率电路。 在实施例中，III-N晶体管架构适于缩放以维持许多连续器件世代的性能改进的轨迹。 在实施例中，III-N晶体管架构适于与IV类晶体管架构（诸如平面和非平面硅CMOS晶体管技术）的单片集成。 具有凹入栅极，对称源极和漏极，再生长源极/漏极中的一个或多个的平面和非平面HEMT实施例使用允许增强模式操作和良好栅极钝化的替代栅极技术形成。

公开(公告)号：WO2012082329A3

公开(公告)日：2012-06-21

申请号：PCT/US2011/061792

申请日：2011-11-22

申请人： INTEL CORPORATION ,  CHU-KUNG, Benjamin ,  DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  MUKHERJEE, Niloy

发明人： CHU-KUNG, Benjamin ,  DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  MUKHERJEE, Niloy

IPC分类号： H01L29/78 ,  H01L21/336

摘要： The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the fabrication of a tunnel field effect transistor having an improved on-current level without a corresponding increasing the off-current level, achieved by the addition of a transition layer between a source and an intrinsic channel of the tunnel field effect transistor.

公开(公告)号：WO0139292A3

公开(公告)日：2011-12-29

申请号：PCT/US0042312

申请日：2000-11-29

申请人： UNIV PENNSYLVANIA ,  JOHNSON ALAN T JR ,  RADOSAVLJEVIC MARKO ,  LEFEBVRE JACQUES

发明人： JOHNSON ALAN T JR ,  RADOSAVLJEVIC MARKO ,  LEFEBVRE JACQUES

IPC分类号： B23B21/00 ,  H01L21/033 ,  H01L21/3213 ,  H01L51/00 ,  H01L51/30 ,  H01L51/40

CPC分类号： H01L21/32139 ,  B82Y10/00 ,  H01L21/0334 ,  H01L51/0021 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/75 ,  Y10S977/752

摘要： A shadow mask method to fabricate electrodes with nanometer scale separation utilizes nanotubes (NTs). Metal wires (4) with gaps are made by incorporating multi-wall carbon nanotubles (1) (MWNTs) or single- wall carbon nanotubes (SWNTs) (or bundles thereof) into a tri-layer electron beam lithography process. The simple, highly controllable, and scaleable method can be used to make gaps with widths between 1 and 100 nm. Electronic transport measurements performed on individual SWNTs bridge nanogaps smaller than 30 nm. Metallic SWNTs exhibits quantum dot behavior with an 80 neV charging energy and a 20 meV energy level splitting. Semiconducting SWNTs show an anomalous field effect transistor behavior.

摘要翻译： 用纳米尺度分离制造电极的荫罩方法使用纳米管（NT）。 具有间隙的金属线（4）通过将多壁碳纳米管（1）（MWNT）或单壁碳纳米管（SWNT）（或其束）并入三层电子束光刻工艺中而制成。 可以使用简单，高度可控和可扩展的方法来形成宽度在1和100nm之间的间隙。 在单个SWNT上执行的电子传输测量桥接小于30nm的纳米膜。 金属SWNTs具有80 neV充电能量和20meV能级分裂的量子点行为。 半导体SWNTs显示出异常的场效应晶体管行为。

公开(公告)号：WO2011087610A2

公开(公告)日：2011-07-21

申请号：PCT/US2010/058784

申请日：2010-12-02

申请人： INTEL CORPORATION ,  KAVALIEROS, Jack, T. ,  RACHMADY, Willy ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  GOE, Niti ,  LEE, Yong Ju ,  MAJHI, Prashant ,  TSAI, Wilman ,  DEWEY, Gilbert

发明人： KAVALIEROS, Jack, T. ,  RACHMADY, Willy ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  GOE, Niti ,  LEE, Yong Ju ,  MAJHI, Prashant ,  TSAI, Wilman ,  DEWEY, Gilbert

CPC分类号： H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

摘要翻译： 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

公开(公告)号：WO2011087609A2

公开(公告)日：2011-07-21

申请号：PCT/US2010058778

申请日：2010-12-02

申请人： INTEL CORP ,  RADOSAVLJEVIC MARKO ,  DEWEY GILBERT ,  MUKHERJEE NILOY ,  PILLARISETTY RAVI

发明人： RADOSAVLJEVIC MARKO ,  DEWEY GILBERT ,  MUKHERJEE NILOY ,  PILLARISETTY RAVI

CPC分类号： H01L29/7782 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848

摘要： Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了将应变传递给诸如水平场效应晶体管的集成电路器件的技术和配置。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡层，耦合到第一阻挡层的量子阱沟道，量子阱沟道包括具有第一晶格常数的第一材料以及耦合到 所述源结构包括具有第二晶格常数的第二材料，其中所述第二晶格常数不同于所述第一晶格常数以在所述量子阱沟道上施加应变。 其他实施例可以被描述和/或要求保护。