公开(公告)号：WO2016160146A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/017870

申请日：2016-02-12

Applicant: INTEL CORPORATION

Inventor： KRIPANIDHI, Arjun ,  PANGAL, Kiran ,  LEEM, Lark-Hoon ,  SRINIVASAN, Balaji

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0066

Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed

Abstract translation: 本公开的实施例描述了在相变存储器中的读取和写入操作以减少突发干扰。 在一个实施例中，一种装置包括读取电路，用于将读取电压施加到相变存储器（PCM）单元，响应于读取电压的应用，将回退脉冲施加到PCM单元，其中挫折脉冲是 对于被配置为将PCM单元从非晶状态转换为结晶状态的规则设定脉冲，对于比第二时间段短的第一时间段执行的更短的设定脉冲，感测电路与应用同时感测 的挫折脉冲，PCM单元是处于非晶态还是结晶状态。 可以描述和/或要求保护其他实施例

公开(公告)号：WO2016025060A1

公开(公告)日：2016-02-18

申请号：PCT/US2015/034290

申请日：2015-06-04

Applicant: INTEL CORPORATION

Inventor： PANDEY, Abhinav ,  BELGAL, Hanmant P. ,  DAMLE, Prashant S. ,  KRIPANIDHI, Arjun ,  URIBE, Sebastian T. ,  LY-GAGNON, Dany-Sebastien ,  RANGAN, Sanjay ,  PANGAL, Kiran

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C7/12 ,  G06F11/1072 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C14/0045 ,  G11C29/028 ,  G11C29/50004 ,  G11C2013/0057 ,  G11C2029/5004

Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.

Abstract translation: 这里描述包括与扩展存储器单元的阈值电压窗口相关联的系统，方法和装置的实施例。 具体地，在一些实施例中，存储器单元可以被配置为通过被设置为设置状态或复位状态来存储数据。 在一些实施例中，可以在读取处理之前在设置状态下对存储器单元执行伪读取处理。 在一些实施例中，可以在复位状态的存储器单元上执行修改的复位算法。 可以描述或要求保护其他实施例。