公开(公告)号：WO2014164099A1

公开(公告)日：2014-10-09

申请号：PCT/US2014/020549

申请日：2014-03-05

Applicant: INTEL CORPORATION ,  PANGAL, Kiran ,  DAMLE, Prashant S. ,  SUNDARAM, Rajesh ,  QAWAMI, Shekoufeh ,  WALKER, Julie M. ,  RIVERS, Doyle

Inventor： PANGAL, Kiran ,  DAMLE, Prashant S. ,  SUNDARAM, Rajesh ,  QAWAMI, Shekoufeh ,  WALKER, Julie M. ,  RIVERS, Doyle

IPC: G06F11/16 ,  G06F12/00

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/27 ,  H03M13/6508

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Abstract translation: 可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误 的存储器阵列。 然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。

公开(公告)号：WO2018004836A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/031985

申请日：2017-05-10

Applicant: INTEL CORPORATION

Inventor： MANTEGAZZA, Davide ,  PAN, Feng ,  DAMLE, Prashant S. ,  BELGAL, Hanmant Pramod ,  PANGAL, Kiran

IPC: G11C13/00

CPC classification number: G11C16/3427 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2013/0052 ,  G11C2013/0057 ,  G11C2013/0092 ,  G11C2213/76 ,  H01L27/2481 ,  H01L45/06

Abstract: A disclosed example to reduce a threshold voltage drift of a selector device of a memory cell includes providing an applied voltage to the selector device of the memory cell, the applied voltage being less than a threshold voltage of the selector device, and reducing the threshold voltage drift of the memory cell by maintaining the applied voltage at the selector device for a thresholding duration to activate the selector device.

Abstract translation: 所公开的用于降低存储器单元的选择器器件的阈值电压漂移的示例包括向存储器单元的选择器器件提供施加的电压，所施加的电压小于阈值电压的阈值电压 通过将选择器装置处施加的电压维持阈值持续时间以激活选择器装置，从而降低存储器单元的阈值电压漂移。

公开(公告)号：WO2017172283A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/020989

申请日：2017-03-06

Applicant: INTEL CORPORATION

Inventor： QAWAMI, Shekoufeh ,  SUNDARAM, Rajesh ,  DAMLE, Prashant S. ,  RIVERS, Doyle ,  WALKER, Julie M.

IPC: G06F13/16

CPC classification number: G11C13/0033 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non- volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non- volatile memory are carried out using the compensated voltage threshold.

Abstract translation: 公开并描述了用于校正非易失性存储器设备中的阈值电压漂移的设备，系统和方法。 在一个示例中，通过基于时间的漂移补偿方案或基于干扰的漂移补偿方案来生成补偿的分界电压，并且使用补偿的电压阈值来执行对非易失性存储器的读取和写入操作。 p>

公开(公告)号：WO2016160158A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/018337

申请日：2016-02-17

Applicant: INTEL CORPORATION

Inventor： MANTEGAZZA, Davide ,  DAMLE, Prashant S. ,  PAGAL, Kiran ,  BELGAL, Hanmant P. ,  PANDEY, Abhinav

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0057 ,  G11C2013/0083

Abstract: Described is an apparatus: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method comprising: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.

Abstract translation: 描述了一种装置：多个存储单元; 偏置逻辑与所述多个存储单元中的至少一个存储单元耦合，所述偏置逻辑用于：将第一读取电压施加到所述至少一个存储单元; 并且向所述至少一个存储单元施加第二读取电压，所述第一读取电压高于所述第二读取电压; 以及第一电路，其可操作以在所述偏置逻辑将所述第一读取电压施加到所述至少一个存储器单元之前，浮动耦合到所述至少一个存储器单元的字线。 一种方法，包括：对至少一个存储单元执行第一读取操作; 以及在所述第一读取操作完成之后对所述至少一个存储器单元执行第二读取操作，其中所述第二读取操作与所述第一读取操作不同。

公开(公告)号：WO2015047334A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/062405

申请日：2013-09-27

Applicant: INTEL CORPORATION ,  KWOK, Zion S. ,  MOTWANI, Ravi H. ,  PANGAL, Kiran ,  DAMLE, Prashant S.

Inventor： KWOK, Zion S. ,  MOTWANI, Ravi H. ,  PANGAL, Kiran ,  DAMLE, Prashant S.

IPC: G06F11/10 ,  G06F12/00

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/108 ,  G06F12/00 ,  G06F2212/7207 ,  G11C29/52 ,  H03M13/1515 ,  H03M13/152

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了存储器中用于纠错的装置，系统和方法。 在一个实施例中，存储器控制器包括接收对存储在存储器中的数据的读取请求的逻辑，检索数据和至少一个相关联的纠错码字，其中数据和相关联的纠错码字分布在多个存储器件 在存储器中，应用第一纠错程序来解码用数据检索的纠错码字，并响应错误校正码字中的不可校正错误，对存储器中的多个设备应用第二纠错例程。 还公开并要求保护其他实施例。

公开(公告)号：WO2016025060A1

公开(公告)日：2016-02-18

申请号：PCT/US2015/034290

申请日：2015-06-04

Applicant: INTEL CORPORATION

Inventor： PANDEY, Abhinav ,  BELGAL, Hanmant P. ,  DAMLE, Prashant S. ,  KRIPANIDHI, Arjun ,  URIBE, Sebastian T. ,  LY-GAGNON, Dany-Sebastien ,  RANGAN, Sanjay ,  PANGAL, Kiran

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C7/12 ,  G06F11/1072 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C14/0045 ,  G11C29/028 ,  G11C29/50004 ,  G11C2013/0057 ,  G11C2029/5004

Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.

Abstract translation: 这里描述包括与扩展存储器单元的阈值电压窗口相关联的系统，方法和装置的实施例。 具体地，在一些实施例中，存储器单元可以被配置为通过被设置为设置状态或复位状态来存储数据。 在一些实施例中，可以在读取处理之前在设置状态下对存储器单元执行伪读取处理。 在一些实施例中，可以在复位状态的存储器单元上执行修改的复位算法。 可以描述或要求保护其他实施例。

公开(公告)号：WO2015138281A1

公开(公告)日：2015-09-17

申请号：PCT/US2015/019366

申请日：2015-03-09

Applicant: INTEL CORPORATION ,  CHU, Daniel J. ,  PANGAL, Kiran ,  FRANKLIN, Nathan R. ,  DAMLE, Prashant S. ,  CHAOHONG, Hu

Inventor： CHU, Daniel J. ,  PANGAL, Kiran ,  FRANKLIN, Nathan R. ,  DAMLE, Prashant S. ,  CHAOHONG, Hu

IPC: G11C13/00 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0061 ,  G11C2013/0047 ,  G11C2013/0052

Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.

Abstract translation: 本公开涉及减轻交叉点存储器中的读取干扰。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括感测模块，其被配置为确定在感测间隔期间是否发生快照事件; 以及写回模块，被配置为如果检测到快照事件，则将逻辑1写回到所述存储器单元。

公开(公告)号：WO2014051775A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/047442

申请日：2013-06-24

Applicant: INTEL CORPORATION ,  PANGAL, Kiran ,  MOTWANI, Ravi H. ,  DAMLE, Prashant S.

Inventor： PANGAL, Kiran ,  MOTWANI, Ravi H. ,  DAMLE, Prashant S.

IPC: G06F12/16 ,  G06F11/10 ,  G11C16/06

CPC classification number: G06F12/0246 ,  G06F11/1012 ,  G06F12/0238 ,  G06F2212/1032 ,  G06F2212/1041 ,  G06F2212/403 ,  G06F2212/7202 ,  G06F2212/7207 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/349

Abstract: Examples are disclosed for techniques associated with protecting system critical data written to non-volatile memory. In some examples, system critical data may be written to a non-volatile memory using a first data protection scheme. User data that includes non-system critical data may also be written to the non-volatile memory using a second data protection scheme. For these examples, both data protection schemes may have a same given data format size. Various examples are provided for use of the first data protection scheme that may provide enhanced protection for the system critical data compared to protection provided to user data using the second data protection scheme. Other examples are described and claimed.

Abstract translation: 公开了与保护写入非易失性存储器的系统关键数据相关的技术的示例。 在一些示例中，可以使用第一数据保护方案将系统关键数据写入非易失性存储器。 包括非系统关键数据的用户数据也可以使用第二数据保护方案写入非易失性存储器。 对于这些示例，两个数据保护方案可以具有相同的给定数据格式大小。 为使用第一数据保护方案提供了各种示例，该方案可以与使用第二数据保护方案提供给用户数据的保护相比提供对系统关键数据的增强保护。 其他的例子被描述和要求保护。