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    METHOD FOR READING A RESISTIVE MEMORY CELL, AND A MEMORY CELL FOR IMPLEMENTATION
    2.
    发明申请
    METHOD FOR READING A RESISTIVE MEMORY CELL, AND A MEMORY CELL FOR IMPLEMENTATION 审中-公开
    方法用于读取电阻式存储单元和细胞为了便于实施

    公开(公告)号：WO2015085977A1

    公开(公告)日：2015-06-18

    申请号：PCT/DE2014000551

    申请日：2014-10-29

    Applicant: FORSCHUNGSZENTRUM JÜLICH GMBH ,  RHEINISCH-WESTFÄLISCHE TECHNISCHE HOCHSCHULE

    Inventor： RHEINISCH-WESTFÄLISCHE TECHNISCHE HOCHSCHULE ,  VAN DEN HURK JAN ,  LINN EIKE ,  WASER RAINER ,  VALOV ILIA

    IPC: F16H48/40

    CPC classification number: G11C13/004 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2213/33 ,  G11C2213/52 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

    Abstract: The invention has involved the development of a method for reading a resistive memory cell that has two electrodes spaced apart from one another by an ion-conductive resistive material and that can be transferred from a stable state having a relatively high resistance value (high resistive state, HRS) to a stable state having a relatively low resistance value (low resistance state, LRS) by applying a write voltage. According to the invention, reading involves a read voltage being applied as a read pulse, wherein the number of ions driven through the ion-conductive resistive material during the pulse is set by means of the level and duration of the pulse such that, on the basis of the state for forming an electrically conductive path through the ion-conductive resistive material, they suffice at least until the onset of a flow of current through this path and hence for the transition to a metastable state VRS (volatile resistance state) with a reduced resistance value and a prescribed relaxation time for the return to the HRS state, but not for the transition to the LRS state. This ensures that the memory cell is always back in the same state after reading as before reading. This renders particularly memory elements that consist of two memory cells in reverse-connected series being nondestructively readable without this diminishing the possibility of producing large arrays from these memory elements.

    Abstract translation: 在本发明，用于读取具有两个电阻式存储器单元的方法，通过离子导电电阻材料的电极，其特征在于通过施加稳定状态的写入电压具有较高的电阻值（高电阻状态，HRS）间隔开的是具有较低电阻值的稳定状态 （低电阻状态，LRS）可变换显影。 根据本发明，将读取电压施加读脉冲，用于读出，其特征在于，设置的通过的数量和脉冲的持续时间的离子导电电阻材料的离子在脉冲期间被驱动的数量，以便开始从状态电阻以形成通过离子传导的导电路径 材料至少直到电流流过该路径，从而过渡到亚稳态的充分降低电阻值和预定的松弛时间为返回到状态HRS，但不为到状态LRS过渡发作（VRS挥发性电阻状态） ， 通过这种方式，确保了读出后的存储器单元肯定是早在相同的条件读数前。 这使得特定存储器元件，其包括两个存储器单元的反串联连接的非破坏性读出而不这降低了实现这些存储元件的大阵列的可能性。

    METHODS OF READING AND USING MEMORY CELLS
    3.
    发明申请
    METHODS OF READING AND USING MEMORY CELLS 审中-公开
    阅读和使用记忆细胞的方法

    公开(公告)号：WO2011037703A2

    公开(公告)日：2011-03-31

    申请号：PCT/US2010/045856

    申请日：2010-08-18

    Applicant: MICRON TECHNOLOGY, INC. ,  SRINIVASAN, Bhaskar ,  SANDHU, Gurtej, S.

    Inventor： SRINIVASAN, Bhaskar ,  SANDHU, Gurtej, S.

    IPC: G11C16/26 ,  G11C16/32 ,  G11C16/10

    CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0061 ,  G11C2013/0052 ,  G11C2213/72

    Abstract: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes.

    Abstract translation: 一些实施例包括读取存储器单元的方法。 存储器单元具有仅在足够的时间长度施加足够的绝对值的电压时发生的写入操作; 并且读取是用太短于持续时间的脉冲来进行的，以足以用于写入操作。 在一些实施例中，用于读取的脉冲可以具有大于或等于用于写入操作的电压的绝对值。 在一些实施例中，存储器单元可以包括非欧姆器件; 如忆阻器和二极管。

    MEMRISTOR ARRAY WITH ACTIVE MEMRISTORS
    6.
    发明申请
    MEMRISTOR ARRAY WITH ACTIVE MEMRISTORS 审中-公开
    具有主动式电位器的磁阻阵列

    公开(公告)号：WO2017014719A1

    公开(公告)日：2017-01-26

    申请号：PCT/US2015/040877

    申请日：2015-07-17

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： STRACHAN, John Paul ,  HU, Miao ,  KUMAR, Suhas

    IPC: G11C11/56 ,  G11C13/00

    CPC classification number: G11C13/0061 ,  G06N3/049 ,  G06N3/0635 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0052 ,  G11C2013/0092

    Abstract: In one example in accordance with the present disclosure a memristor device is described. The device includes an active memristor to be set to one of a plurality of states. The device also includes a state controller to program the state of the active memristor. The state defines a current-voltage relationship for the active memristor. The state controller also sets an operating point for the active memristor around which an input signal oscillates. The resistance of the active memristor defines an amplitude modulation of the input signal and the reactance of the active memristor defines a phase delay of the input signal.

    Abstract translation: 在根据本公开的一个示例中，描述了忆阻器装置。 该装置包括被设置为多个状态之一的有效忆阻器。 该器件还包括一个状态控制器，用于对活性忆阻器的状态进行编程。 该状态定义了有源忆阻器的电流 - 电压关系。 状态控制器还为有源忆阻器设置一个输入信号振荡的工作点。 有源忆阻器的电阻定义了输入信号的幅度调制，有源忆阻器的电抗定义了输入信号的相位延迟。

    INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB
    8.
    发明申请
    INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB 审中-公开
    集成的SETBACK读取与减少的反应障碍

    公开(公告)号：WO2016160146A1

    公开(公告)日：2016-10-06

    申请号：PCT/US2016/017870

    申请日：2016-02-12

    Applicant: INTEL CORPORATION

    Inventor： KRIPANIDHI, Arjun ,  PANGAL, Kiran ,  LEEM, Lark-Hoon ,  SRINIVASAN, Balaji

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0066

    Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed

    Abstract translation: 本公开的实施例描述了在相变存储器中的读取和写入操作以减少突发干扰。 在一个实施例中，一种装置包括读取电路，用于将读取电压施加到相变存储器（PCM）单元，响应于读取电压的应用，将回退脉冲施加到PCM单元，其中挫折脉冲是 对于被配置为将PCM单元从非晶状态转换为结晶状态的规则设定脉冲，对于比第二时间段短的第一时间段执行的更短的设定脉冲，感测电路与应用同时感测 的挫折脉冲，PCM单元是处于非晶态还是结晶状态。 可以描述和/或要求保护其他实施例

    CURRENT BEHAVIOR OF ELEMENTS
    9.
    发明申请
    CURRENT BEHAVIOR OF ELEMENTS 审中-公开
    元素的当前行为

    公开(公告)号：WO2016018281A1

    公开(公告)日：2016-02-04

    申请号：PCT/US2014/048800

    申请日：2014-07-30

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： BUCHANAN, Brent

    IPC: G11C5/14 ,  G11C7/06

    CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0061 ,  G11C16/10 ,  G11C29/026 ,  G11C29/028 ,  G11C2013/0052 ,  G11C2213/15

    Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is coupled to an element whose status is to be determined, and the first module is to receive an input current that increases over time. The second module is to perform a temporal derivative of a voltage across the element. The third module is to provide an output signal based on a current behavior of the element, according to a change in voltage as a function of a change in current.

    Abstract translation: 根据本公开的一个方面的示例性设备包括第一模块，第二模块和第三模块。 第一模块耦合到要确定其状态的元件，并且第一模块将接收随时间增加的输入电流。 第二个模块是执行跨元件的电压的时间导数。 第三模块是根据电流的变化作为电流变化的函数，基于元件的电流行为来提供输出信号。

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