公开(公告)号：WO2016160158A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/018337

申请日：2016-02-17

Applicant: INTEL CORPORATION

Inventor： MANTEGAZZA, Davide ,  DAMLE, Prashant S. ,  PAGAL, Kiran ,  BELGAL, Hanmant P. ,  PANDEY, Abhinav

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0057 ,  G11C2013/0083

Abstract: Described is an apparatus: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method comprising: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.

Abstract translation: 描述了一种装置：多个存储单元; 偏置逻辑与所述多个存储单元中的至少一个存储单元耦合，所述偏置逻辑用于：将第一读取电压施加到所述至少一个存储单元; 并且向所述至少一个存储单元施加第二读取电压，所述第一读取电压高于所述第二读取电压; 以及第一电路，其可操作以在所述偏置逻辑将所述第一读取电压施加到所述至少一个存储器单元之前，浮动耦合到所述至少一个存储器单元的字线。 一种方法，包括：对至少一个存储单元执行第一读取操作; 以及在所述第一读取操作完成之后对所述至少一个存储器单元执行第二读取操作，其中所述第二读取操作与所述第一读取操作不同。

公开(公告)号：WO2018125602A1

公开(公告)日：2018-07-05

申请号：PCT/US2017/066546

申请日：2017-12-14

Applicant: INTEL CORPORATION

Inventor： CONNOR, Christopher F. ,  QUERBACH, Bruce ,  BELGAL, Hanmant P.

IPC: G11C16/26 ,  G11C16/10 ,  G06F12/02

CPC classification number: G11C13/004 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0038 ,  G11C16/26 ,  G11C16/3418 ,  G11C2013/0052

Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.

公开(公告)号：WO2016025060A1

公开(公告)日：2016-02-18

申请号：PCT/US2015/034290

申请日：2015-06-04

Applicant: INTEL CORPORATION

Inventor： PANDEY, Abhinav ,  BELGAL, Hanmant P. ,  DAMLE, Prashant S. ,  KRIPANIDHI, Arjun ,  URIBE, Sebastian T. ,  LY-GAGNON, Dany-Sebastien ,  RANGAN, Sanjay ,  PANGAL, Kiran

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C7/12 ,  G06F11/1072 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C14/0045 ,  G11C29/028 ,  G11C29/50004 ,  G11C2013/0057 ,  G11C2029/5004

Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.

Abstract translation: 这里描述包括与扩展存储器单元的阈值电压窗口相关联的系统，方法和装置的实施例。 具体地，在一些实施例中，存储器单元可以被配置为通过被设置为设置状态或复位状态来存储数据。 在一些实施例中，可以在读取处理之前在设置状态下对存储器单元执行伪读取处理。 在一些实施例中，可以在复位状态的存储器单元上执行修改的复位算法。 可以描述或要求保护其他实施例。