公开(公告)号：WO2018026476A2

公开(公告)日：2018-02-08

申请号：PCT/US2017/041606

申请日：2017-07-11

Applicant: INTEL CORPORATION

Inventor： WU, Wei ,  ZOU, Yi ,  KHAN, Jawad B. ,  GUO, Xin

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56

CPC classification number: G06F3/0616 ,  G06F3/0644 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the nonvolatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group.

Abstract translation: 提供了用于编程多单元存储单元组的设备，方法和系统。 非易失性存储器具有存储单元。 使用多个阈值电压电平利用信息对每个存储单元进行编程，并且根据来自多个页面的位来编程每个存储单元。 存储器控制器被配置为对存储单元进行编程并将非易失性存储器中的存储单元组织成存储单元组。 每个存储单元组存储多个信息位，并且每个存储单元组中的每个存储单元被编程有多个阈值电压电平。 存储器控制器从页中选择要写入一个存储单元组的位，并确定要用于存储单元组中的每个存储单元的至少一个阈值电压电平，以对存储单元组中的所选位进行编程。

公开(公告)号：WO2017105775A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/062849

申请日：2016-11-18

Applicant: INTEL CORPORATION

Inventor： WU, Wei ,  TOMISHIMA, Shigeki ,  LU, Shih-Lien L.

IPC: G06F13/36 ,  G06F9/38

CPC classification number: G11C7/06 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4282 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/40618 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/107

Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

Abstract translation: 提供了存储设备和存储体，其包括全局数据总线和分为两部分的本地数据总线，其中本地数据总线可配置为将信号引导至全局数据总线。 还提供了一种方法，其中信号在分为两部分的本地数据总线中被接收，并且信号从本地数据总线被引导到全局数据总线。 还提供由处理器和存储设备组成的计算设备。

公开(公告)号：WO2018026475A3

公开(公告)日：2018-02-08

申请号：PCT/US2017/041603

申请日：2017-07-11

Applicant: INTEL CORPORATION

Inventor： WU, Wei ,  ZOU, Yi ,  KHAN, Jawad B. ,  GUO, Xin

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26

Abstract: Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.

公开(公告)号：WO2017105773A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/062834

申请日：2016-11-18

Applicant: INTEL CORPORATION

Inventor： WU, Wei ,  TOMISHIMA, Shigeki ,  LU, Shih-Lien L.

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F13/1668 ,  G11C5/025 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1048 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/107

Abstract: Provided are a memory device and a memory bank comprised of a local data bus, a segmented global data bus coupled to the local data bus, and a section select switch that is configurable to direct a signal from the local data bus to either end of the segmented global data bus. Provided also is a computational device comprising a processor and the memory device and optionally a display. Provided also is a method in which a signal is received from a local data bus, and a section select switch is configured to direct the signal from the local data bus to either end of a segmented global data bus.

Abstract translation: 提供了由本地数据总线，耦合到本地数据总线的分段全局数据总线以及可配置为引导来自所述本地数据总线的信号的段选择开关的存储设备和存储体， 本地数据总线到分段全局数据总线的任一端。 还提供了一种包括处理器和存储器设备以及可选的显示器的计算设备。 还提供了一种方法，其中从本地数据总线接收信号，并且区段选择开关被配置为将信号从本地数据总线引导到分段全局数据总线的任一端。

公开(公告)号：WO2016209393A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/031895

申请日：2016-05-11

Applicant: INTEL CORPORATION

Inventor： AUGUSTINE, Charles ,  TOMISHIMA, Shigeki ,  WU, Wei ,  LU, Shih-Lien ,  TSCHANZ, James W. ,  PANAGOPOULOS, Georgios ,  NAEIMI, Helia

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Abstract translation: 描述了一种包括具有电阻存储单元的半导体芯片存储器阵列的装置。 该装置还包括比较器，用于将写入阵列的第一个字与存储在阵列中的第二个字进行比较，该第二个字由写入操作所指向的位置将第一个字写入数组。 该装置还包括用于迭代地写入一个或多个比特位置的电路​​，其中在每个连续的迭代中随着写入电流强度的增加而在第一个字和第二个字之间存在差异。

公开(公告)号：WO2022139849A1

公开(公告)日：2022-06-30

申请号：PCT/US2020/067075

申请日：2020-12-26

Applicant: INTEL CORPORATION

Inventor： AGARWAL, Rajat ,  CHEN, Hsing-Min ,  CHEN, Wei P. ,  WU, Wei ,  LING, Jing ,  BAINS, Kuljit ,  CRISS, Kjersten E. ,  BUCH, Deep K. ,  YIGZAW, Theodros ,  HOLM, John G ,  RUDOFF, Andrew M. ,  SINGH, Vaibhav ,  MANDAVA, Sreenivas

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C29/00

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：WO2022066317A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/046178

申请日：2021-08-16

Applicant: INTEL CORPORATION

Inventor： OH, Byoungchan ,  WU, Wei

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/15

Abstract: Examples include techniques to improve implement an error correction codeword (ECC) scheme to protect data stored to a memory from both hard and random bit errors using a hybrid ECC scheme that includes generation of first and second codewords to protect the data.

公开(公告)号：WO2018057896A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/052965

申请日：2017-09-22

Applicant: INTEL CORPORATION

Inventor： WU, Wei ,  AUGUSTINE, Charles ,  PAUL, Somnath

IPC: G06N3/063 ,  G11C11/413

Abstract: Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows and columns of memory cells. There is one row of the rows for each of a plurality of neurons and columns for each of a plurality of time slots. Indication is made in a current column in the row of the memory cells for a firing neuron that a spike was fired. Indication is made in the current column in rows of memory cells of idle neurons that did not fire that a spike was not fired. Information in the array is used to determine a timing difference between a connected neuron and the firing neuron and to adjust a weight of the connecting synapse.

Abstract translation: 提供了一种神经形态计算设备，存储设备，系统和方法，用于维持尖峰神经网络中的神经元的尖峰历史。 在具有存储器单元的行和列的阵列的存储器装置中产生神经网络尖峰历史。 针对多个时隙中的每一个的多个神经元和列中的每一个存在一行的行。 在发射峰值的发射神经元的存储器单元的行中的当前列中进行指示。 在当前列中指示闲置神经元的存储器单元行中没有触发尖峰未被触发的指示。 阵列中的信息用于确定连接的神经元和发射神经元之间的时间差，并调整连接突触的重量。

公开(公告)号：WO2017074648A1

公开(公告)日：2017-05-04

申请号：PCT/US2016/055033

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： WU, Wei ,  AUGUSTINE, Charles ,  TOMISHIMA, Shigeki ,  LU, Shih-Lien L. ,  TSCHANZ, James W.

IPC: G06F11/10

CPC classification number: H03M13/05 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/353 ,  H03M13/611

Abstract: In one embodiment, temperature dependent, multiple mode error correction in accordance with one aspect of this disclosure, is employed for a memory circuit containing arrays of memory cells. In one embodiment, a temperature sensor coupled to an array is configured to provide an output signal which is a function of the temperature of the array of memory cells. Multiple mode error correction code (ECC) logic having an input coupled to an output of the temperature sensor, is configured to encode write data and decode read data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells. Other aspects are described herein.

Abstract translation: 在一个实施例中，根据本公开的一个方面的温度相关的多模式误差校正被用于包含存储器单元阵列的存储器电路。 在一个实施例中，耦合到阵列的温度传感器被配置为提供输出信号，该输出信号是存储器单元阵列的温度的函数。 具有耦合到温度传感器的输出的输入的多模式错误校正码（ECC）逻辑被配置为对错误校正码中的存储器单元阵列的读取数据进行编码写入数据和解码读取数据，其中多个错误校正 模式作为存储器单元阵列的温度的函数。 其他方面在这里描述。

公开(公告)号：WO2016209586A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/035513

申请日：2016-06-02

Applicant: INTEL CORPORATION

Inventor： NAEIMI, Helia ,  WU, Wei ,  TOMISHIMA, Shigeki ,  LU, Shih-Lien

IPC: G11C29/12 ,  G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1048 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/52 ,  G11C2029/0411

Abstract: Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.

Abstract translation: 一些实施例包括具有从存储器单元接收信息的接口的设备和方法，所述存储器单元被配置为具有多个状态以指示存储在存储器单元中的信息的值;以及控制单元，用于监视从存储器检索的信息中的错误 细胞。 基于信息中的错误，控制单元生成控制信息以使存储单元从多个状态之间的状态变为附加状态。 附加状态与多个状态不同。