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    VERTICAL TRANSISTOR-BASED LOGIC GATE
    3.
    发明申请
    VERTICAL TRANSISTOR-BASED LOGIC GATE 审中-公开

    公开(公告)号：WO2019132883A1

    公开(公告)日：2019-07-04

    申请号：PCT/US2017/068549

    申请日：2017-12-27

    Applicant: INTEL CORPORATION

    Inventor： NIKONOV, Dmitri, E. ,  MANIPATRUNI, Sasikanth ,  MORROW, Patrick ,  YOUNG, Ian, A.

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/105

    Abstract: Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first metal layer; a first channel of a semiconductor material on top of the first metal layer, both ends of the semiconductor material doped of a first type; a first gate dielectric adjacent the first channel; and a first plurality of gates arranged radially around the first channel and in contact with the first gate dielectric to separately control the first channel.

    PERPENDICULAR MAGNET ANISOTROPY BASED SPIN HALL MEMORY USING SPIN ORBIT EFFECT
    5.
    发明申请
    PERPENDICULAR MAGNET ANISOTROPY BASED SPIN HALL MEMORY USING SPIN ORBIT EFFECT 审中-公开
    使用旋转轨道效应的基于垂直磁极各向异性的自旋霍尔存储器

    公开(公告)号：WO2017222521A1

    公开(公告)日：2017-12-28

    申请号：PCT/US2016/038803

    申请日：2016-06-22

    Applicant: INTEL CORPORATION

    Inventor： MANIPATRUNI, Sasikanth ,  NIKONOV, Dmitri ,  CAUDILLO, Roman ,  LIN, Chia-Ching ,  YOUNG, Ian, A.

    IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10

    CPC classification number: H01L43/02 ,  H01L43/08 ,  H01L43/10

    Abstract: An apparatus is provided which comprises: a magnetic junction having a free magnet layer which has perpendicular magnetic anisotropy (PMA), wherein the free magnet layer has anisotropy axis perpendicular to a plane of a device; and interconnect formed of a spin orbit material which is to provide spin current polarized perpendicular to an interface of the interconnect, wherein the interconnect is adjacent to the free magnet layer of the magnetic junction. An apparatus is provided which comprises: a magnet layer having PMA; and a layer formed of an interface normal spin orbit material, the layer being adjacent to one end of the magnet layer. Other embodiments may be described and/or claimed.

    Abstract translation: 提供了一种装置，其包括：具有垂直磁各向异性（PMA）的自由磁层的磁性结，其中自由磁层具有垂直于器件平面的各向异性轴; 以及由自旋轨道材料形成的互连，所述自旋轨道材料提供垂直于所述互连的界面极化的自旋电流，其中所述互连与所述磁性结的自由磁体层相邻。 提供了一种装置，其包括：具有PMA的磁体层; 以及由界面法线自旋轨道材料形成的层，所述层与磁体层的一端相邻。 其他实施例可以被描述和/或要求保护。

    MULTI-LEVEL SPIN BUFFER AND INVERTER
    7.
    发明申请
    MULTI-LEVEL SPIN BUFFER AND INVERTER 审中-公开
    多级自缓冲器和逆变器

    公开(公告)号：WO2017111877A1

    公开(公告)日：2017-06-29

    申请号：PCT/US2015/000513

    申请日：2015-12-24

    Applicant: INTEL CORPORATION

    Inventor： MANIPATRUNI, Sasikanth ,  YOUNG, Ian, A. ,  NIKONOV, Dmitri, E. ,  AVCI, Uygar, E. ,  MORROW, Patrick ,  CHAUDHRY, Anurag

    IPC: H01L43/02 ,  H01L43/10 ,  G11C11/02 ,  G11C11/16

    CPC classification number: H03K19/20 ,  B82Y25/00 ,  G11C11/16 ,  H03K19/0002 ,  H03K19/02 ,  H03K19/16

    Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

    Abstract translation: 描述的是一种装置，其包括：4态输入磁体; 与所述四态输入磁体相邻的第一自旋通道区域; 一个4态输出磁体; 与所述四态输入和输出磁体相邻的第二自旋通道区域; 以及与所述四态输出磁体相邻的第三自旋通道区域。 在一种装置中描述，该装置包括：4态输入磁体; 与所述四态输入磁体相邻的第一滤波器层; 与所述第一滤光层相邻的第一自旋通道区域; 一个4态输出磁体; 邻近所述四态输出磁体的第二滤波器层; 与所述第一和第二滤光层相邻的第二自旋通道区域; 以及与第二滤光层相邻的第三自旋通道区域。

    PHASE INTERPOLATOR
    9.
    发明申请
    PHASE INTERPOLATOR 审中-公开
    相位插补器

    公开(公告)号：WO2007075312A2

    公开(公告)日：2007-07-05

    申请号：PCT/US2006/047110

    申请日：2006-12-08

    Applicant: INTEL CORPORATION ,  FAN, Yongping ,  YOUNG, Ian, A.

    Inventor： FAN, Yongping ,  YOUNG, Ian, A.

    IPC: H03K5/13

    CPC classification number: H03H11/16 ,  H04L7/0338

    Abstract: A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs of the current drivers are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first and second signals.

    Abstract translation: 相位插值器包括产生具有第一相位延迟的第一信号和具有第二相位延迟的第二信号和相位混频器的第一电路。 耦合相位混合器以接收来自第一电路的第一和第二信号。 相位混合器包括多个电流驱动器，每个电流驱动器包括耦合以选择性地延迟第一或第二信号中的一个的电流驱动器输入和耦合以输出相位延迟信号的电流驱动器输出。 电流驱动器的当前驱动器输出耦合在一起以组合来自电流驱动器的相位延迟信号，以产生具有从第一和第二信号内插的相位的输出相位延迟信号。

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