公开(公告)号：WO1992020100A1

公开(公告)日：1992-11-12

申请号：PCT/US1991005365

申请日：1991-07-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BAKHRU, Nanik ,  BATES, Richard, Allen ,  CZORNYJ, George ,  DIPAOLO, Nunzio ,  KUMAR, Ananda, Hosakere ,  MUKKAVILLI, Suryanarayana ,  STEIMEL, Heinz, Otto ,  TUMMALA, Rao, Ramamohana

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/481 ,  H01L21/4853 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S428/901 ,  Y10T428/239 ,  Y10T428/24802 ,  Y10T428/24917 ,  H01L2924/00

Abstract: Disclosed is a ceramic substrate having a protective coating on at least one surface thereof which includes: a ceramic substrate (52) having at least one electrically conductive via (54) extending to a surface of the substrate; an electrically conductive I/O pad (56) electrically connected to at least one of the vias; an I/O pin (58) brazed to the I/O pad (56), the brazed pin having a braze fillet (60); and a protective layer of polymeric material (62) fully encapsulating the I/O pad, wherein the layer of polymeric material protects the I/O pad, from corrosion. Also disclosed is a method of protecting a ceramic substrate from corrosion, the ceramic substrate of the type having a plurality of electrically conductive vias extending to a surface of the substrate, a multilayer metallic I/O pad electrically connected to at least one of the vias, and an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet, the method comprising the step of: encapsulating fully the I/O pad with a protective layer of polymeric material wherein the layer of polymeric material protects the I/O pad from corrsoion. In a preferred embodiment, the I/O pin is selectively exposed to plasma ashing to remove any errant polymeric material from the pin shank, thereby assuring electrical contact to the pin shank.

公开(公告)号：WO1992009102A1

公开(公告)日：1992-05-29

申请号：PCT/US1991000703

申请日：1991-02-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHANG, Kenneth ,  CZORNYJ, George ,  FAROOQ, Mukta, Shaji ,  KUMAR, Ananda, Hosakere ,  PITTLER, Marvin, S. +di ,  STEIMEL, Heinz, Otto

IPC: H01L21/48

CPC classification number: H01L21/76808 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/76807 ,  H01L2221/1031 ,  H01L2221/1036 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/184 ,  H05K3/388 ,  H05K3/465 ,  H05K3/4661 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/107

Abstract: A method of making a multilayer thin film structure on the surface of a dielectric substrate which includes the steps of: a) forming a multilayer thin film structure including the steps of: applying a first layer of dielectric polymeric material on the surface of a dielectric substrate, applying a second layer of dielectric polymeric material over the first layer of polymeric material wherein the second polymeric material is photosensitive, imagewise exposing and developing the second polymeric material to form a feature therein, the second layer feature in communication with at least one feature formed in the first polymeric material; and b) filling the features in the entire multilayer structure simultaneously with conductive material. Preferably, the first layer feature is a via and the second layer feature is a capture pad or wiring channel. Also disclosed is a multilayer thin film structure made by this method.

Abstract translation: 一种在电介质基板的表面上制造多层薄膜结构的方法，包括以下步骤：a）形成多层薄膜结构，其包括以下步骤：将第一层电介质聚合物材料施加到介电基片的表面上 在所述第一聚合物材料层上施加第二层电介质聚合材料，其中所述第二聚合物材料是光敏的，成像曝光和显影所述第二聚合物材料以在其中形成特征，所述第二层特征与形成的至少一个特征相连通 在第一种聚合材料中; 以及b）与导电材料同时填充整个多层结构中的特征。 优选地，第一层特征是通孔，第二层特征是捕获垫或布线通道。 还公开了通过该方法制造的多层薄膜结构。

公开(公告)号：WO1991016725A1

公开(公告)日：1991-10-31

申请号：PCT/US1990005802

申请日：1990-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHANG, Kenneth ,  CZORNYJ, George ,  KUMAR, Ananda, H. ,  STEIMEL, Heinz, O.

IPC: H01L21/48

CPC classification number: H01L21/4846 ,  H05K3/107 ,  H05K3/143 ,  H05K3/4644 ,  Y10S430/146

Abstract: The present invention provides a packaging semiconductor structure and method for obtaining same. The structure is comprised of at least one level of dielectric and metallurgy layers. The at least one level is comprised of a wiring metallurgy (18) plane and a 'through-via' plane of interconnecting metallurgy in association with both one and two layers of polymeric dielectric materials (13, 19). The self-alignment method of fabrication of the level provides a streamlined technique wherein stringent masking and alignment requirements are relaxed, undue processing such as at least one polishing step is eliminated and a structure having adhesive integrity is fabricated.