公开(公告)号：WO2022245889A1

公开(公告)日：2022-11-24

申请号：PCT/US2022/029752

申请日：2022-05-18

Applicant: ATOMERA INCORPORATED

Inventor： MEARS, Robert, J. ,  TAKEUCHI, Hideki

IPC: H01L29/08 ,  H01L29/15 ,  H01L21/336 ,  H01L29/775 ,  H01L29/423 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/165

Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and including a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

公开(公告)号：WO2022240713A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/028260

申请日：2022-05-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： SADOVNIKOV, Alexei ,  HAYNIE, Sheldon, Douglas ,  RADHAKRISHNA, Ujwal

IPC: H01L29/40 ,  H01L29/78 ,  H01L2223/6672 ,  H01L23/647 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A microelectronic device (100) includes a doped region (110) of semiconductor material (104) having a first region (116) and an opposite second region (120). The microelectronic device (100) is configured to provide a first operational potential at the first region (116) and to provide a second operational potential at the second region (120). The microelectronic device (100) includes field plate segments (140) in trenches (124) extending into the doped region (110). Each field plate segment (140) is separated from the semiconductor material (104) by a trench liner (128) of dielectric material. The microelectronic device (100) further includes circuitry (158) electrically connected to each of the field plate segments (140). The circuitry (158) is configured to apply bias potentials to the field plate segments (140). The bias potentials are monotonic with respect to distances of the field plate segments (140) from the first region (116) of the doped region (110).

公开(公告)号：WO2022177683A1

公开(公告)日：2022-08-25

申请号：PCT/US2022/012756

申请日：2022-01-18

Applicant: QUALCOMM INCORPORATED

Inventor： YANG, Bin ,  LI, Xia ,  YANG, Haining

IPC: H01L29/165 ,  H01L21/336 ,  H01L29/78

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge) (SiGe) buffer layer with a SiGe source (211S) and drain (211D) having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET (200) on a SiGe buffer layer (214) rather than directly on a Si substrate (216) and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

公开(公告)号：WO2019082220A1

公开(公告)日：2019-05-02

申请号：PCT/IT2018/050203

申请日：2018-10-21

Applicant: DADDI, Valentina

Inventor： DADDI, Valentina

IPC: H01L29/739 ,  H01L29/165 ,  H01L29/10

Abstract: This document defines the characteristics of Hybrid Insulated Gate Multi-structure and multi-material Transistor, that is to say "Hybrid IGMT", as power electronics transistor. This transistor is characterized with a structure of internal conduction substrate composed of vertical channels, distinguishing between channels with high electrical conductivity and insulated channels. This peculiarity distinguishes Hybrid IGMT from any other power electronics transistor and brings many advantages, most of all the significant reduction, till absence, of switching losses. Within description a specific implementation of conductive channels is introduced, consisting in a composite structure called "Si // C", which allows the fulfillment of constant and very low conduction power losses in a wide operating electrical and thermal range. Hybrid IGMT is intended for application in vehicle electric traction, also in low-voltage or medium- voltage electric systems requiring DC-AC or AC-DC conversion with high stability, long operating life and low power losses.

公开(公告)号：WO2011034750A1

公开(公告)日：2011-03-24

申请号：PCT/US2010/047957

申请日：2010-09-07

Applicant: SANDISK 3D LLC ,  BANDYOPADHYAY, Abhijit ,  HOU, Kun ,  MAXWELL, Steven

Inventor： BANDYOPADHYAY, Abhijit ,  HOU, Kun ,  MAXWELL, Steven

IPC: H01L29/165 ,  H01L29/45 ,  H01L29/868

CPC classification number: H01L29/868 ,  H01L27/2409 ,  H01L27/2481 ,  H01L29/165 ,  H01L29/452 ,  H01L29/456 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

Abstract: A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

Abstract translation: 半导体p-i-n二极管及其形成方法在此描述。 在一个方面，在被掺杂为具有一个导电性（p +或n +）和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻，这可能增加正向偏置电流。 掺杂区域延伸到SiGe区域的下方，使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域之下的掺杂区域可以用于保持反向偏置电流不增加，这是由于添加的SiGe区域的结果。 在一个实施例中，SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配，这可以在这些二极管与 3D存储器阵列中的R / W材料。

公开(公告)号：WO2008091972A1

公开(公告)日：2008-07-31

申请号：PCT/US2008/051852

申请日：2008-01-24

Applicant: MEARS TECHNOLOGIES, INC. ,  RAO, Kalipatnam Vivek

Inventor： RAO, Kalipatnam Vivek

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15

CPC classification number: H01L29/154 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66643

Abstract: A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

Abstract translation: 可以包括半导体层的半导体器件和它们之间的超晶格界面层。 超晶格界面层可以包括多个堆叠的层组。 每组层可以包括限定基底半导体部分的多个层叠的基底半导体单层，以及约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。 来自相对的基底半导体部分的至少一些原子可以与穿过至少一个介入的非半导体单层的化学键化学地结合在一起。

公开(公告)号：WO2007126495A1

公开(公告)日：2007-11-08

申请号：PCT/US2007/004689

申请日：2007-02-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred ,  JAVORKA, Peter ,  BLOOMQUIST, Joe

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred ,  JAVORKA, Peter ,  BLOOMQUIST, Joe

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/665 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: By recessing (112D, 212D) drain and source regions (114, 214), a highly stressed layer (118, 218), such as a contact etch stop layer, may be formed in the recess (112, 212) in order to enhance the strain generation in the adjacent channel region (104, 204) of a field effect transistor (100, 200). Moreover, a strained semiconductor material (230) may be positioned in close proximity to the channel region (104, 204) by reducing or avoiding undue relaxation effects of metal suicides (217), thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain- inducing mechanism.

Abstract translation: 通过凹陷（112D，212D）漏极和源极区域（114,214），可以在凹部（112,212）中形成高应力层（118,218），例如接触蚀刻停止层，以便增强 在场效应晶体管（100,200）的相邻沟道区（104,204）中产生应变。 此外，应变半导体材料（230）可以通过减少或避免金属硅化物（217）的不适当的松弛效应来定位在通道区域（104,204）附近，从而也为应变产生提供更高的效率。 在一些方面，两种效应可以组合以获得更有效的应变诱导机制。

公开(公告)号：WO2007027186A1

公开(公告)日：2007-03-08

申请号：PCT/US2005/032526

申请日：2005-09-12

Applicant: M.E.C. TECHNOLOGY, INC. ,  KULKASKI, Richard ,  ALLISON, Robert, William, Jr. ,  SHAPOVAL, Sergei Yur'evich ,  POWELL, Michael, William

Inventor： KULKASKI, Richard ,  ALLISON, Robert, William, Jr. ,  SHAPOVAL, Sergei Yur'evich ,  POWELL, Michael, William

IPC: H01L27/15 ,  H01L29/165 ,  H01L31/153 ,  H01L29/18 ,  H01L29/20 ,  H01L29/22

CPC classification number: H01L33/20 ,  H01L33/38 ,  H01L33/44 ,  H01L33/46 ,  H01L33/58 ,  H01L33/60

Abstract: A semiconductor device and a method of forming the semiconductor device. The semiconductor device may include a substrate 110; an n-layer 130; a buffer 120 formed between the substrate and the n-layer; an active heterostructure 150 including a plurality of quantum wells and being proximate to the n-layer; and a p-layer 160 proximate to the active heterostructure. The buffer, n-layer, active heterostructure, and p-layer may sequentially form a mesa-shaped structure. The method may include the steps of pre-cleaning a substrate; sequentially forming an n-layer, an active layer, and a p-layer on the substrate; depositing a mirror atop the p-layer; etching a mesa profile of sequentially decreasing width for the n-layer, the active layer, the p-layer, and the mirror; and depositing side mirrors 190 along sides of the mesa profile.

Abstract translation: 半导体器件和形成半导体器件的方法。 半导体器件可以包括衬底110; n层130; 在衬底和n层之间形成的缓冲器120; 包括多个量子阱并且靠近n层的有源异质结构150; 以及靠近有源异质结构的p层160。 缓冲层，n层，活性异质结构和p层可以顺序地形成台面状结构。 该方法可以包括预清洁衬底的步骤; 在衬底上依次形成n层，有源层和p层; 在p层顶上沉积镜子; 蚀刻n层，有源层，p层和反射镜的顺序减小宽度的台面轮廓; 以及沿着台面轮廓的侧面沉积侧镜190。

公开(公告)号：WO2006064290A1

公开(公告)日：2006-06-22

申请号：PCT/GB2005/050250

申请日：2005-12-14

Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG ,  ELLIS, John, Nigel

Inventor： ELLIS, John, Nigel

IPC: H01L29/737 ,  H01L29/165 ,  H01L21/331

CPC classification number: H01L29/7378

Abstract: A bipolar transistor is formed on a heavily doped silicon substrate (1). An epitaxially grown collector (12) is formed on the substrate (1) and comprises silicon containing germanium at least at the top of the collector (12). An epitaxial base (13) is formed on the collector (12) to have the opposite polarity and also comprises silicon containing germanium at least at the bottom of the base (13). An emitter is formed at the top of the base (13) and comprises poly silicon doped to have the same polarity as the collector (12).

Abstract translation: 在重掺杂硅衬底（1）上形成双极晶体管。 在衬底（1）上形成外延生长的收集器（12），并且至少在收集器（12）的顶部包括含硅的锗。 在集电器（12）上形成具有相反极性的外延基极（13），并且至少在基底（13）的底部还包含含硅的锗。 发射极形成在基极（13）的顶部，并且包括被掺杂以具有与集电极（12）相同极性的多晶硅。

公开(公告)号：WO2004053929A3

公开(公告)日：2005-01-27

申请号：PCT/US0325174

申请日：2003-08-12

Applicant: MASSACHUSETTS INST TECHNOLOGY ,  KIM SUNGJEE ,  BAWENDI MOUNGI G

Inventor： KIM SUNGJEE ,  BAWENDI MOUNGI G

IPC: C04B41/46 ,  C09K11/00 ,  C09K11/88 ,  C30B7/00 ,  C30B29/10 ,  C30B29/60 ,  C30B33/00 ,  D02G3/00 ,  G01N33/543 ,  G01N33/58 ,  G09G3/34 ,  H01L20060101 ,  H01L21/20 ,  H01L21/208 ,  H01L21/368 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/225 ,  H01L29/267 ,  H01L31/00

CPC classification number: G01N33/588 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y20/00 ,  B82Y30/00 ,  C09K11/883 ,  C30B7/00 ,  C30B29/605 ,  C30B33/00 ,  H01L21/0237 ,  H01L21/02409 ,  H01L21/02411 ,  H01L21/02521 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/02601 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/205 ,  H01L29/225 ,  H01L29/267 ,  H01L51/426 ,  Y02E10/549 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/777 ,  Y10S977/811 ,  Y10T428/12021 ,  Y10T428/12528 ,  Y10T428/12986 ,  Y10T428/294 ,  Y10T428/2991 ,  Y10T428/315

Abstract: A semiconductor nanocrystal heterostructure has a core of a first semiconductor material surrounded by an overcoating of a second semiconductor material. Upon excitation, one carrier can be substantially confined to the core and 5 the other carrier can be substantially confined to the overcoating.

Abstract translation: 半导体纳米晶异质结构具有由第二半导体材料的外涂层包围的第一半导体材料的芯。 在激发时，一个载体可以基本上限制在核心上，另一个载体可以基本上限于外涂层。