公开(公告)号：WO2020061484A1

公开(公告)日：2020-03-26

申请号：PCT/US2019/052208

申请日：2019-09-20

Applicant: LAM RESEARCH CORPORATION

Inventor： SINGHAL, Akhil N. ,  AUSTIN, Dustin Zachary ,  GANANY, Alon ,  BOATRIGHT, Daniel

IPC: H01L21/3213 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67 ,  H05H1/46

Abstract: Various embodiments include methods and chemistries to etch metal-oxide films. In one embodiment, a method of etching tin oxide (SnO 2 ) films includes using thionyl chloride (SOCl 2 ) chemistry to produce an etch rate of the SnO 2 films of up to 10-times higher as compared with Cl 2 chemistry for similar flow-rates and process conditions, and gettering oxygen species from the SnO 2 films by using the SOCl 2 , thereby forming volatile SO 2 and volatile SnCl 4 to provide human safety and machine safety and operations. Other methods, chemistries, and techniques are disclosed.

公开(公告)号：WO2021150331A1

公开(公告)日：2021-07-29

申请号：PCT/US2020/065717

申请日：2020-12-17

Applicant: LAM RESEARCH CORPORATION

Inventor： GANANY, Alon ,  AUSTIN, Dustin Zachary ,  BATZER, Rachel ,  SINGHAL, Akhil

IPC: H01J37/32 ,  C23C16/44

Abstract: Processing methods and apparatus for depositing a protective layer on internal surfaces of a reaction chamber are provided. One method may include depositing, while no wafers are present in the reaction chamber having interior surfaces, a first layer of protective material onto the interior surfaces, the interior surfaces comprising a first material, processing, after the depositing the first layer, a portion of a batch of wafers within a reaction chamber, measuring an amount of the first material in the reaction chamber during processing the portion of the batch of wafers, or on one of the wafers in the portion of the batch of wafers, determining that the first amount exceeds a threshold, and depositing, in response to determining that the first amount exceeds the threshold and while no wafers are present in the reaction chamber, a second layer of protective material onto the interior surfaces of the reaction chamber.

公开(公告)号：WO2023283144A1

公开(公告)日：2023-01-12

申请号：PCT/US2022/036026

申请日：2022-07-01

Applicant: LAM RESEARCH CORPORATION

Inventor： KUMAR, Ravi ,  AGARWAL, Pulkit ,  LAVOIE, Adrien ,  AUSTIN, Dustin Zachary ,  ABEL, Joseph R. ,  AGNEW, Douglas Walter ,  BAKER, Jonathan Grant

IPC: H01L21/02 ,  H01L21/768 ,  C23C16/455 ,  C23C16/04 ,  C23C16/505 ,  C23C16/30 ,  C23C16/56

Abstract: A method comprising: providing a substrate in a processing station comprising a substrate support and a showerhead, the substrate comprising a gap to be filled; and depositing silicon-containing film in the gap by a plasma-enhanced atomic layer deposition (PEALD) process comprising multiple cycles of operations (a)-(d): (a) a dose operation comprising flowing a silicon-containing precursor into the processing station via the showerhead to allow the silicon-containing precursor to adsorb onto the substrate; (b) after (a), flowing a purge gas into the processing station; (c) after (b), exposing the substrate to plasma species to react with the adsorbed silicon-containing precursor; and (d) after (c), flowing a purge gas into the processing station, wherein the silicon-containing precursor continues to flow into the processing station during at least (b).

公开(公告)号：WO2021202808A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/025271

申请日：2021-03-31

Applicant: LAM RESEARCH CORPORATION

Inventor： AUSTIN, Dustin Zachary ,  CURTIN, Ian John ,  ABEL, Joseph R. ,  VAN SCHRAVENDIJK, Bart J. ,  VARADARAJAN, Seshasayee ,  LAVOIE, Adrien ,  FIELDS, Jeremy David ,  AGARWAL, Pulkit ,  BHANDARI, Shiva Sharan

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/455 ,  H01L21/762 ,  H01L27/115

Abstract: Methods of filling a gap with a dielectric material including using an inhibitor plasma during deposition. The inhibitor plasma increases a nucleation barrier of the deposited film. When the inhibitor plasma interacts with material in the feature, the material at the bottom of the feature receives less plasma treatment than material located closer to a top portion of the feature or in field. Deposition at the top of the feature is then selectively inhibited and deposition in lower portions of the feature proceeds with less inhibition or without being inhibited. As a result, bottom-up fill is enhanced, which can create a sloped profile that mitigates the seam effect and prevents void formation. In some embodiments, an underlying material at the top of the feature is protected using an integrated liner. In some embodiments, a hydrogen chemistry is used during gap fill to reduce seam formation.

公开(公告)号：WO2022020528A1

公开(公告)日：2022-01-27

申请号：PCT/US2021/042652

申请日：2021-07-21

Applicant: LAM RESEARCH CORPORATION

Inventor： GUPTA, Awnish ,  VAN SCHRAVENDIJK, Bart J. ,  PASQUALE, Frank Loren ,  LAVOIE, Adrien ,  VARNELL, Jason Alexander ,  RAMASAGARAM, Praneeth ,  ABEL, Joseph R. ,  PETRAGLIA, Jennifer Leigh ,  AUSTIN, Dustin Zachary

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/56

Abstract: Methods and apparatuses for depositing dielectric films into features on semiconductor substrates are described herein. Methods involve depositing dielectric films by using controlled thermal chemical vapor deposition, with periodic passivation operations and densification to modulate film properties.

公开(公告)号：WO2022006010A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/039444

申请日：2021-06-28

Applicant: LAM RESEARCH CORPORATION

Inventor： ABEL, Joseph R. ,  VAN SCHRAVENDIJK, Bart J. ,  CURTIN, Ian John ,  AGNEW, Douglas Walter ,  AUSTIN, Dustin Zachary ,  GUPTA, Awnish

IPC: H01L21/768 ,  H01L21/02 ,  C23C16/04 ,  C23C16/0245 ,  C23C16/0272 ,  C23C16/345 ,  C23C16/401 ,  C23C16/45534 ,  C23C16/45542 ,  C23C16/5096

Abstract: Methods of forming air gaps in hole and trench structures are disclosed. The methods may be used to form buried voids, i.e., voids for which the top is below the top of the adjacent features. The methods include inhibition of the hole or trench structures and selective deposition at the top of the structure forming an air gap within the structures. In some embodiments, the methods are to reduce intra-level capacitance in semiconductor devices.